loadpatents
name:-0.010755062103271
name:-0.017184972763062
name:-0.013046979904175
Gentner; Thomas Patent Filings

Gentner; Thomas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gentner; Thomas.The latest application filed is for "integrated circuit with optical tunnel".

Company Profile
9.12.9
  • Gentner; Thomas - Boeblingen DE
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Integrated circuit with optical tunnel
Grant 11,239,152 - Torreiter , et al. February 1, 2
2022-02-01
Continuous mutual extended processor self-test
Grant 11,074,147 - Bergmann , et al. July 27, 2
2021-07-27
Integrated Circuit With Optical Tunnel
App 20210066183 - Torreiter; Otto Andreas ;   et al.
2021-03-04
ATE compatible high-efficient functional test
Grant 10,768,232 - Gentner , et al. Sep
2020-09-08
Constrained pseudorandom test pattern for in-system logic built-in self-test
Grant 10,746,790 - Cook Lobo , et al. A
2020-08-18
Functional testing of high-speed serial links
Grant 10,684,930 - Eckert , et al.
2020-06-16
Continuous Mutual Extended Processor Self-test
App 20200174901 - Bergmann; Tobias Ulrich ;   et al.
2020-06-04
Functional Testing Of High-speed Serial Links
App 20190163596 - Eckert; Martin ;   et al.
2019-05-30
On-chip hardware-controlled window strobing
Grant 10,288,684 - Gentner , et al.
2019-05-14
On-chip hardware-controlled window strobing
Grant 10,281,527 - Gentner , et al.
2019-05-07
Ate Compatible High-efficient Functional Test
App 20190018061 - Gentner; Thomas ;   et al.
2019-01-17
On-chip Hardware-controlled Window Strobing
App 20180364308 - Gentner; Thomas ;   et al.
2018-12-20
On-chip Hardware-controlled Window Strobing
App 20180364309 - Gentner; Thomas ;   et al.
2018-12-20
Layout effect characterization for integrated circuits
Grant 10,114,914 - Eckert , et al. October 30, 2
2018-10-30
Layout Effect Characterization For Integrated Circuits
App 20180107771 - Eckert; Martin ;   et al.
2018-04-19
Layout effect characterization for integrated circuits
Grant 9,904,748 - Eckert , et al. February 27, 2
2018-02-27
Layout effect characterization for integrated circuits
Grant 9,740,813 - Eckert , et al. August 22, 2
2017-08-22
Testing an integrated circuit
Grant 9,354,275 - Akdemir , et al. May 31, 2
2016-05-31
Integrated circuit failure prediction using clock duty cycle recording and analysis
Grant 9,319,030 - Gentner , et al. April 19, 2
2016-04-19
Integrated Circuit Failure Prediction Using Clock Duty Cycle Recording And Analysis
App 20150171835 - Gentner; Thomas ;   et al.
2015-06-18
Testing An Integrated Circuit
App 20140351664 - Akdemir; Birol ;   et al.
2014-11-27

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