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Gemelli; Riccardo Patent Filings

Gemelli; Riccardo

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gemelli; Riccardo.The latest application filed is for "functional safety method, corresponding system-on-chip, device and vehicle".

Company Profile
9.19.17
  • Gemelli; Riccardo - Carugate IT
  • GEMELLI; Riccardo - Carugate MI
  • Gemelli; Riccardo - Settimo Milanese N/A IT
  • Gemelli; Riccardo - Settimo M.se N/A IT
  • Gemelli; Riccardo - Settimo M.se (Milano) IT
  • Gemelli; Riccardo - Settimo Milanese Mi
  • Gemelli; Riccardo - S. Colombano/L IT
  • Gemelli; Riccardo - Milan IT
  • Gemelli; Riccardo - S. Colombano IT
  • Gemelli; Riccardo - San Colombano IT
  • Gemelli, Riccardo - Milano IT
  • Gemelli, Riccardo - S. Colombano/L - MI IT
  • Gemelli, Riccardo - San Colombano/L IT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Functional safety method, corresponding system-on-chip, device and vehicle
Grant 11,436,162 - Gemelli , et al. September 6, 2
2022-09-06
Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM)
Grant 11,055,173 - Ranjan , et al. July 6, 2
2021-07-06
Memory architecture including response manager for error correction circuit
Grant 10,860,415 - Ranjan , et al. December 8, 2
2020-12-08
Functional Safety Method, Corresponding System-on-chip, Device And Vehicle
App 20200379924 - Gemelli; Riccardo ;   et al.
2020-12-03
Redundant Storage Of Error Correction Code (ecc) Checkbits For Validating Proper Operation Of A Static Random Access Memory (sra
App 20200110663 - RANJAN; Om ;   et al.
2020-04-09
Redundant storage of error correction code (ECC) checkbits for validating proper operation of a static random access memory (SRAM)
Grant 10,528,422 - Ranjan , et al. J
2020-01-07
Memory Architecture Including Response Manager For Error Correction Circuit
App 20190317851 - RANJAN; Om ;   et al.
2019-10-17
Memory architecture including response manager for error correction circuit
Grant 10,379,937 - Ranjan , et al. A
2019-08-13
Redundant Storage Of Error Correction Code (ecc) Checkbits For Validating Proper Operation Of A Static Random Access Memory (sra
App 20190146868 - Ranjan; Om ;   et al.
2019-05-16
Memory Architecture Including Response Manager For Error Correction Circuit
App 20190129790 - Ranjan; Om ;   et al.
2019-05-02
Functional Safety Method, System, And Corresponding Computer Program Product
App 20190098327 - Marinelli; Nicola ;   et al.
2019-03-28
Update of a cumulative residence time of a packet in a packet-switched communication network
Grant 9,203,725 - Ronchetti , et al. December 1, 2
2015-12-01
Device and method for switching data traffic in a digital transmission network
Grant 9,154,446 - Gemelli , et al. October 6, 2
2015-10-06
Transmission of parallel data flows on a parallel bus
Grant 8,594,136 - Cucchi , et al. November 26, 2
2013-11-26
Device And Method For Switching Data Traffic In A Digital Transmission Network
App 20130182716 - Gemelli; Riccardo ;   et al.
2013-07-18
Equipment protection method and apparatus
Grant 8,429,511 - Cucchi , et al. April 23, 2
2013-04-23
Update Of A Cumulative Residence Time Of A Packet In A Packet-switched Communication Network
App 20130028265 - Ronchetti; Luigi ;   et al.
2013-01-31
Transmission Of Parallel Data Flows On A Parallel Bus
App 20110268133 - Cucchi; Silvio ;   et al.
2011-11-03
Equipment protection method and apparatus
App 20100138711 - Cucchi; Silvio ;   et al.
2010-06-03
Method and device for routing or compressing packets destination address containing classless address
Grant 7,289,502 - Gemelli , et al. October 30, 2
2007-10-30
Interface bus protocol for managing transactions in a system of distributed microprocessor interfaces toward marco-cell based designs implemented as ASIC or FPGA bread boarding
Grant 7,130,942 - Gemelli , et al. October 31, 2
2006-10-31
Automated method for generating the cyclic redundancy check for transmission of multi-protocol packets
Grant 7,082,563 - Gemelli , et al. July 25, 2
2006-07-25
Clock generation system for a prototyping apparatus
Grant 7,036,095 - Pavesi , et al. April 25, 2
2006-04-25
System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol
Grant 6,970,966 - Gemelli , et al. November 29, 2
2005-11-29
Daughter board for a prototyping system
Grant 6,964,574 - Pavesi , et al. November 15, 2
2005-11-15
System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative COMMON BUS protocol
App 20050165995 - Gemelli, Riccardo ;   et al.
2005-07-28
Automated method for generating the cyclic redundancy check, or CRC, particularly for the transmission of multi-protocol packets in packet-switching networks
App 20040172582 - Gemelli, Riccardo ;   et al.
2004-09-02
Daughter board for a prototyping system
App 20040066615 - Pavesi, Marco ;   et al.
2004-04-08
System of distributed microprocessor interfaces toward macro-cell based designs implemented as ASIC or FPGA bread boarding and relative common bus protocol
App 20030101307 - Gemelli, Riccardo ;   et al.
2003-05-29
Clock generation system for a prototyping apparatus
App 20030074637 - Pavesi, Marco ;   et al.
2003-04-17

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