loadpatents
name:-0.041597127914429
name:-0.024300098419189
name:-0.015520095825195
Geetha; Vedaraman Patent Filings

Geetha; Vedaraman

Patent Applications and Registrations

Patent applications and USPTO patent grants for Geetha; Vedaraman.The latest application filed is for "method and system for performing data movement operations with read snapshot and in place write update".

Company Profile
18.25.47
  • Geetha; Vedaraman - Fremont CA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method And System For Performing Data Movement Operations With Read Snapshot And In Place Write Update
App 20220261351 - Vasudevan; Anil ;   et al.
2022-08-18
Method and system for performing data movement operations with read snapshot and in place write update
Grant 11,327,894 - Vasudevan , et al. May 10, 2
2022-05-10
High Performance Interconnect
App 20220114122 - Safranek; Robert J. ;   et al.
2022-04-14
Multiple dies hardware processors and methods
Grant 11,294,852 - Nassif , et al. April 5, 2
2022-04-05
High performance interconnect
Grant 11,269,793 - Safranek , et al. March 8, 2
2022-03-08
Multiple Dies Hardware Processors And Methods
App 20220050805 - NASSIF; NEVINE ;   et al.
2022-02-17
High Performance Interconnect
App 20210117350 - Safranek; Robert J. ;   et al.
2021-04-22
Method And System For Performing Data Movement Operations With Read Snapshot And In Place Write Update
App 20210049102 - Vasudevan; Anil ;   et al.
2021-02-18
High Performance Interconnect
App 20200356502 - Safranek; Robert J. ;   et al.
2020-11-12
Hybrid Directory And Snoopy-based Coherency To Reduce Directory Update Overhead In Two-level Memory
App 20200356482 - Geetha; Vedaraman ;   et al.
2020-11-12
Multiple Dies Hardware Processors And Methods
App 20200334196 - NASSIF; NEVINE ;   et al.
2020-10-22
Multiple dies hardware processors and methods
Grant 10,795,853 - Nassif , et al. October 6, 2
2020-10-06
Clock signal modulation for processors
Grant 10,782,729 - Fahim , et al. Sept
2020-09-22
Method and system for performing data movement operations with read snapshot and in place write update
Grant 10,606,755 - Vasudevan , et al.
2020-03-31
High Performance Interconnect
App 20190391939 - Safranek; Robert J. ;   et al.
2019-12-26
Mission-critical computing architecture
Grant 10,514,990 - Fahim , et al. Dec
2019-12-24
Selective memory mode authorization enforcement
Grant 10,379,768 - Natu , et al. A
2019-08-13
Mission-critical Computing Architecture
App 20190163583 - Fahim; Bahaa ;   et al.
2019-05-30
Clock Signal Modulation for Processors
App 20190163229 - Fahim; Bahaa ;   et al.
2019-05-30
High performance interconnect
Grant 10,248,591 - Safranek , et al.
2019-04-02
Value of forward state by increasing local caching agent forwarding
Grant 10,204,049 - Geetha , et al. Feb
2019-02-12
Method And System For Performing Data Movement Operations With Read Snapshot And In Place Write Update
App 20190004958 - Vasudevan; Anil ;   et al.
2019-01-03
Two level memory full line writes
Grant 10,140,213 - Blankenship , et al. Nov
2018-11-27
Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device
Grant 10,042,562 - Geetha , et al. August 7, 2
2018-08-07
Implementation of reserved cache slots in computing system having inclusive/non inclusive tracking and two level system memory
Grant 10,007,606 - Geetha , et al. June 26, 2
2018-06-26
Multiple Dies Hardware Processors And Methods
App 20180101502 - NASSIF; NEVINE ;   et al.
2018-04-12
Selective Memory Mode Authorization Enforcement
App 20180095692 - NATU; Mahesh S. ;   et al.
2018-04-05
Value Of Forward State By Increasing Local Caching Agent Forwarding
App 20180081808 - GEETHA; Vedaraman ;   et al.
2018-03-22
Apparatus And Method For A Non-power-of-2 Size Cache In A First Level Memory Device To Cache Data Present In A Second Level Memory Device
App 20180004433 - GEETHA; Vedaraman ;   et al.
2018-01-04
Two Level Memory Full Line Writes
App 20170337134 - Blankenship; Robert G. ;   et al.
2017-11-23
Implementation of Reserved Cache Slots in Computing System Having Inclusive/Non Inclusive Tracking And Two Level System Memory
App 20170286298 - GEETHA; Vedaraman ;   et al.
2017-10-05
Apparatus and method for a non-power-of-2 size cache in a first level memory device to cache data present in a second level memory device
Grant 9,747,041 - Geetha , et al. August 29, 2
2017-08-29
Cpu remote snoop filtering mechanism for field programmable gate array
App 20170185515 - Fahim; Bahaa ;   et al.
2017-06-29
Apparatus And Method For A Non-power-of-2 Size Cache In A First Level Memory Device To Cache Data Present In A Second Level Memory Device
App 20170185315 - Geetha; Vedaraman ;   et al.
2017-06-29
High Performance Interconnect
App 20170109315 - Safranek; Robert J. ;   et al.
2017-04-20
High Performance Interconnect Coherence Protocol
App 20170109286 - Blankenship; Robert G. ;   et al.
2017-04-20
High performance interconnect
Grant 9,626,321 - Safranek , et al. April 18, 2
2017-04-18
Method, apparatus and system for optimizing cache memory transaction handling in a processor
Grant 9,606,925 - Fahim , et al. March 28, 2
2017-03-28
Two Level Memory Full Line Writes
App 20160283388 - Blankenship; Robert G. ;   et al.
2016-09-29
Method, Apparatus And System For Optimizing Cache Memory Transaction Handling In A Processor
App 20160283382 - Fahim; Bahaa ;   et al.
2016-09-29
Cache coherency apparatus and method minimizing memory writeback operations
Grant 9,436,605 - Chamberlain , et al. September 6, 2
2016-09-06
Inclusive and non-inclusive tracking of local cache lines to avoid near memory reads on cache line memory writes into a two level system memory
Grant 9,418,009 - Moga , et al. August 16, 2
2016-08-16
Method, apparatus and system for handling cache misses in a processor
Grant 9,405,687 - Fahim , et al. August 2, 2
2016-08-02
Inclusive/Non Inclusive Tracking of Local Cache Lines To Avoid Near Memory Reads On Cache Line Memory Writes Into A Two Level System Memory
App 20150186275 - Moga; Adrian C. ;   et al.
2015-07-02
Cache Coherency Apparatus And Method Minimizing Memory Writeback Operations
App 20150178206 - Chamberlain; Jeffrey D. ;   et al.
2015-06-25
Method, Apparatus And System For Handling Cache Misses In A Processor
App 20150127907 - Fahim; Bahaa ;   et al.
2015-05-07
High Performance Interconnect Coherence Protocol
App 20150081984 - Blankenship; Robert G. ;   et al.
2015-03-19
Mechanism To Improve Input/output Write Bandwidth In Scalable Systems Utilizing Directory Based Coherecy
App 20140281270 - Neefs; Henk G. ;   et al.
2014-09-18
High Performance Interconnect Coherence Protocol
App 20140201463 - Blankenship; Robert G. ;   et al.
2014-07-17
High Performance Interconnect
App 20140112339 - Safranek; Robert J. ;   et al.
2014-04-24
Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines
Grant 8,631,210 - Moga , et al. January 14, 2
2014-01-14
Dynamically routing data responses directly to requesting processor core
Grant 8,495,091 - Baum , et al. July 23, 2
2013-07-23
Allocation And Write Policy For A Glueless Area-efficient Directory Cache For Hotly Contested Cache Lines
App 20130185522 - MOGA; ADRIAN C. ;   et al.
2013-07-18
Allocation and write policy for a glueless area-efficient directory cache for hotly contested cache lines
Grant 8,392,665 - Moga , et al. March 5, 2
2013-03-05
Opportunistic Snoop Broadcast (osb) In Directory Enabled Home Snoopy Systems
App 20130007376 - KOTTAPALLI; SAILESH ;   et al.
2013-01-03
Dynamically Routing Data Responses Directly To Requesting Processor Core
App 20130007046 - Baum; Allen J. ;   et al.
2013-01-03
Allocation And Write Policy For A Glueless Area-efficient Directory Cache For Hotly Contested Cache Lines
App 20120079214 - Moga; Adrian C. ;   et al.
2012-03-29

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed