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Patent applications and USPTO patent grants for Geer; Charles Porter.The latest application filed is for "architecture for a physical interface of a high speed front side bus".
Patent | Date |
---|---|
Architecture for a physical interface of a high speed front side bus Grant 7,945,805 - Baumgartner , et al. May 17, 2 | 2011-05-17 |
Dynamic clock phase alignment between independent clock domains Grant 7,904,741 - Baumgartner , et al. March 8, 2 | 2011-03-08 |
Dynamic clock phase alignment between independent clock domains Grant 7,716,514 - Baumgartner , et al. May 11, 2 | 2010-05-11 |
Architecture for a physical interface of a high speed front side bus Grant 7,624,297 - Baumgartner , et al. November 24, 2 | 2009-11-24 |
Architecture for a Physical Interface of a High Speed Front Side Bus App 20080147952 - Baumgartner; Steven John ;   et al. | 2008-06-19 |
Architecture for a Physical Interface of a High Speed Front Side Bus App 20080148088 - Baumgartner; Steven John ;   et al. | 2008-06-19 |
Dynamic Clock Phase Alignment Between Independent Clock Domains App 20080126566 - Baumgartner; Steven John ;   et al. | 2008-05-29 |
Dynamic Clock Phase Alignment Between Independent Clock Domains App 20080072093 - Baumgartner; Steven John ;   et al. | 2008-03-20 |
Clock frequency detect with programmable jitter tolerance Grant 7,129,757 - Geer , et al. October 31, 2 | 2006-10-31 |
Clock frequency detect with programmable jitter tolerance App 20060114032 - Geer; Charles Porter ;   et al. | 2006-06-01 |
Dynamic repair of redundant memory array Grant 6,181,614 - Aipperspach , et al. January 30, 2 | 2001-01-30 |
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