Gasanov; Elyar E.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Gasanov; Elyar E..The latest application filed is for "systems and methods for rank deficient encoding".
Company Profile
0.62.42
- Gasanov; Elyar E. - Moscow RU
- GASANOV, ELYAR E. - MOSKVA RU
Patent Activity
| Patent | Date |
|---|---|
| Systems and methods for area efficient data encoding Grant 9,331,716 - Panteleev , et al. May 3, 2 | 2016-05-03 |
| Parallel decoder for multiple wireless standards Grant 9,319,181 - Sokolov , et al. April 19, 2 | 2016-04-19 |
| Systems and Methods for Rank Deficient Encoding App 20150229333 - Alekseev; Dmitriy V. ; et al. | 2015-08-13 |
| Systems and Methods for Area Efficient Data Encoding App 20150229331 - Panteleev; Pavel A. ; et al. | 2015-08-13 |
| Programmable circuit for high speed computation of the interleaver tables for multiple wireless standards Grant 8,938,654 - Sokolov , et al. January 20, 2 | 2015-01-20 |
| Optimization of data processors with irregular patterns Grant 8,923,413 - Shutkin , et al. December 30, 2 | 2014-12-30 |
| No-delay microsequencer Grant 8,868,890 - Shutkin , et al. October 21, 2 | 2014-10-21 |
| Two-pass linear complexity task scheduler Grant 8,850,437 - Shutkin , et al. September 30, 2 | 2014-09-30 |
| L-value generation in a decoder Grant 8,842,784 - Sokolov , et al. September 23, 2 | 2014-09-23 |
| Radix-4 Viterbi Forward Error Correction Decoding App 20140223267 - Gasanov; Elyar E. ; et al. | 2014-08-07 |
| Radix-4 viterbi forward error correction decoding Grant 8,775,914 - Gasanov , et al. July 8, 2 | 2014-07-08 |
| Variable parity encoder Grant 8,775,893 - Panteleev , et al. July 8, 2 | 2014-07-08 |
| Branch metrics calculation for multiple communications standards Grant 8,699,396 - Panteleev , et al. April 15, 2 | 2014-04-15 |
| Reconfigurable encoding per multiple communications standards Grant 8,700,969 - Panteleev , et al. April 15, 2 | 2014-04-15 |
| Timer manager architecture based on binary heap Grant 8,656,206 - Gasanov , et al. February 18, 2 | 2014-02-18 |
| High Speed Add-compare-select Circuit App 20140040342 - Sokolov; Andrey P. ; et al. | 2014-02-06 |
| Reconfigurable BCH decoder Grant 8,621,329 - Panteleev , et al. December 31, 2 | 2013-12-31 |
| Parallel true random number generator architecture Grant 8,539,009 - Aliseychik , et al. September 17, 2 | 2013-09-17 |
| Optimization of Data Processors with Irregular Patterns App 20130235907 - Shutkin; Yurii S. ; et al. | 2013-09-12 |
| System and method for using the universal multipole for the implementation of a configurable binary Bose-Chaudhuri-Hocquenghem (BCH) encoder with variable number of errors Grant 8,527,851 - Andreev , et al. September 3, 2 | 2013-09-03 |
| BCH or reed-solomon decoder with syndrome modification Grant 8,397,143 - Neznanov , et al. March 12, 2 | 2013-03-12 |
| Soft reed-solomon decoder based on error-and-erasure reed-solomon decoder Grant 8,365,054 - Gasanov , et al. January 29, 2 | 2013-01-29 |
| Variable Parity Encoder App 20130019139 - Panteleev; Pavel A. ; et al. | 2013-01-17 |
| Two-pass Linear Complexity Task Scheduler App 20120284731 - Shutkin; Yurii S. ; et al. | 2012-11-08 |
| Parallel Decoder For Multiple Wireless Standards App 20120281790 - Sokolov; Andrey P. ; et al. | 2012-11-08 |
| Timer Manager Architecture Based On Binary Heap App 20120278648 - Gasanov; Elyar E. ; et al. | 2012-11-01 |
| Scheme for erasure locator polynomial calculation in error-and-erasure decoder Grant 8,286,060 - Panteleev , et al. October 9, 2 | 2012-10-09 |
| Computation Of Jacobian Logarithm Operation App 20120166501 - Sokolov; Andrey P. ; et al. | 2012-06-28 |
| Radix-4 Viterbi Forward Error Correction Decoding App 20120144274 - Gasanov; Elyar E. ; et al. | 2012-06-07 |
| Branch Metrics Calculation For Multiple Communications Standards App 20120134325 - Panteleev; Pavel A. ; et al. | 2012-05-31 |
| Reconfigurable Encoding Per Multiple Communications Standards App 20120137190 - Panteleev; Pavel A. ; et al. | 2012-05-31 |
| L-value Generation In A Decoder App 20120128102 - Sokolov; Andrey P. ; et al. | 2012-05-24 |
| Configurable Reed-Solomon decoder based on modified Forney syndromes Grant 8,181,096 - Andreev , et al. May 15, 2 | 2012-05-15 |
| No-delay Microsequencer App 20120117359 - Shutkin; Yurii S. ; et al. | 2012-05-10 |
| Reconfigurable Bch Decoder App 20120054586 - Panteleev; Pavel A. ; et al. | 2012-03-01 |
| Programmable Circuit For High Speed Computation Of The Interleaver Tables For Multiple Wireless Standards App 20110239079 - Sokolov; Andrey P. ; et al. | 2011-09-29 |
| Bch Or Reed-solomon Decoder With Syndrome Modification App 20100299580 - Neznanov; Ilya V. ; et al. | 2010-11-25 |
| Soft Reed-solomon Decoder Based On Error-and-erasure Reed-solomon Decoder App 20100281344 - Gasanov; Elyar E. ; et al. | 2010-11-04 |
| Low area architecture in BCH decoder Grant 7,823,050 - Gasanov , et al. October 26, 2 | 2010-10-26 |
| Parallel True Random Number Generator Architecture App 20100153478 - Aliseychik; Pavel A. ; et al. | 2010-06-17 |
| System and method for using the universal multipole for the implementation of a configurable binary bose-chaudhuri-hocquenghem (BCH) encoder with variable number of errors App 20100031126 - Andreev; Alexander E. ; et al. | 2010-02-04 |
| Scheme For Erasure Locator Polynomial Calculation In Error-and-erasure Decoder App 20100031127 - Panteleev; Pavel A. ; et al. | 2010-02-04 |
| Ramptime propagation on designs with cycles Grant 7,568,175 - Zolotykh , et al. July 28, 2 | 2009-07-28 |
| Configurable Reed-solomon Decoder Based On Modified Forney Syndromes App 20090158118 - Andreev; Alexander ; et al. | 2009-06-18 |
| Method of selecting cells in logic restructuring Grant 7,496,870 - Lyalin , et al. February 24, 2 | 2009-02-24 |
| Method and apparatus for controlling congestion during integrated circuit design resynthesis Grant 7,401,313 - Galatenko , et al. July 15, 2 | 2008-07-15 |
| Method and apparatus for performing logical transformations for global routing Grant 7,398,486 - Galatenko , et al. July 8, 2 | 2008-07-08 |
| Low Area Architecture in BCH Decoder App 20080155381 - Gasanov; Elyar E. ; et al. | 2008-06-26 |
| Ramptime Propagation On Designs With Cycles App 20070234255 - Zolotykh; Andrej A. ; et al. | 2007-10-04 |
| Multiple buffer insertion in global routing Grant 7,257,791 - Galatenko , et al. August 14, 2 | 2007-08-14 |
| Ramptime propagation on designs with cycles Grant 7,246,336 - Zolotykh , et al. July 17, 2 | 2007-07-17 |
| Method and apparatus for controlling congestion during integrated circuit design resynthesis App 20070094631 - Galatenko; Alexei V. ; et al. | 2007-04-26 |
| Method Of Selecting Cells In Logic Restructuring App 20070050744 - Lyalin; Iliya V. ; et al. | 2007-03-01 |
| Method of selecting cells in logic restructuring Grant 7,146,591 - Lyalin , et al. December 5, 2 | 2006-12-05 |
| Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths Grant 7,111,267 - Gasanov , et al. September 19, 2 | 2006-09-19 |
| Process and apparatus for placement of megacells in ICs design Grant 7,103,865 - Galatenko , et al. September 5, 2 | 2006-09-05 |
| Ramptime propagation on designs with cycles App 20060123369 - Zolotykh; Andrej A. ; et al. | 2006-06-08 |
| Method of selecting cells in logic restructuring App 20060112361 - Lyalin; Iliya V. ; et al. | 2006-05-25 |
| Multiple buffer insertion in global routing App 20060112363 - Galatenko; Alexei V. ; et al. | 2006-05-25 |
| Process and apparatus to assign coordinates to nodes of logical trees without increase of wire lengths App 20060048087 - Gasanov; Elyar E. ; et al. | 2006-03-02 |
| Method and apparatus for finding optimal unification substitution for formulas in technology library Grant 7,003,739 - Gasanov , et al. February 21, 2 | 2006-02-21 |
| Method and apparatus for performing logical transformations for global routing App 20050210422 - Galatenko, Alexei V. ; et al. | 2005-09-22 |
| Process and apparatus for placement of megacells in ICs design App 20050114813 - Galatenko, Alexei V. ; et al. | 2005-05-26 |
| Method and apparatus for finding optimal unification substitution for formulas in technology library App 20050114804 - Gasanov, Elyar E. ; et al. | 2005-05-26 |
| Method to find boolean function symmetries Grant 6,868,536 - Gasanov , et al. March 15, 2 | 2005-03-15 |
| Multidirectional router Grant 6,845,495 - Andreev , et al. January 18, 2 | 2005-01-18 |
| Process of restructuring logics in ICs for setup and hold time optimization Grant 6,810,515 - Lu , et al. October 26, 2 | 2004-10-26 |
| Method to find boolean function symmetries App 20040098676 - Gasanov, Elyar E. ; et al. | 2004-05-20 |
| Process of restructuring logics in ICs for setup and hold time optimization App 20040060012 - Lu, Aiguo ; et al. | 2004-03-25 |
| Floor plan tester for integrated circuit design Grant 6,701,493 - Gasanov , et al. March 2, 2 | 2004-03-02 |
| Overlap remover manager Grant 6,701,503 - Nikitin , et al. March 2, 2 | 2004-03-02 |
| Method and apparatus for dynamic buffer and inverter tree optimization Grant 6,681,373 - Zolotykh , et al. January 20, 2 | 2004-01-20 |
| Method and apparatus for quick search for identities applicable to specified formula Grant 6,637,011 - Zolotykh , et al. October 21, 2 | 2003-10-21 |
| Assignment of cell coordinates Grant 6,637,016 - Gasanov , et al. October 21, 2 | 2003-10-21 |
| Floor plan tester for integrated circuit design App 20030188274 - Gasanov, Elyar E. ; et al. | 2003-10-02 |
| Cell placement in integrated circuit chips to remove cell overlap, row overflow and optimal placement of dual height cells Grant 6,629,304 - Gasanov , et al. September 30, 2 | 2003-09-30 |
| Blocked net buffer insertion Grant 6,615,401 - Gasanov , et al. September 2, 2 | 2003-09-02 |
| Overlap remover manager App 20030149952 - Nikitin, Andrey A. ; et al. | 2003-08-07 |
| Multidirectional router App 20030121017 - Andreev, Alexandre E. ; et al. | 2003-06-26 |
| Timing recomputation Grant 6,553,551 - Zolotykh , et al. April 22, 2 | 2003-04-22 |
| Changing clock delays in an integrated circuit for skew optimization Grant 6,550,045 - Lu , et al. April 15, 2 | 2003-04-15 |
| Method in integrating clock tree synthesis and timing optimization for an integrated circuit design Grant 6,550,044 - Pavisic , et al. April 15, 2 | 2003-04-15 |
| Parallelization Of Resynthesis App 20020162085 - Zolotykh, Andrej A. ; et al. | 2002-10-31 |
| Parallelization of resynthesis Grant 6,470,487 - Zolotykh , et al. October 22, 2 | 2002-10-22 |
| Method and apparatus for parallel simultaneous global and detail routing Grant 6,324,674 - Andreev , et al. November 27, 2 | 2001-11-27 |
| Method And Apparatus For Parallel Simultaneous Global And Detail Routing App 20010018759 - ANDREEV, ALEXANDER E. ; et al. | 2001-08-30 |
| Net routing using basis element decomposition Grant 6,253,363 - Gasanov , et al. June 26, 2 | 2001-06-26 |
| Method and apparatus for hierarchical global routing descend Grant 6,175,950 - Scepanovic , et al. January 16, 2 | 2001-01-16 |
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