Garni; Bradley J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Garni; Bradley J..The latest application filed is for "bypass system and method that mimics clock to data memory read timing".

Company Profile

0.16.12

Garni; Bradley J. - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Bypass system and method that mimics clock to data memory read timing Grant 9,263,100 - Garni , et al. February 16, 2	2016-02-16
Bypass System And Method That Mimics Clock To Data Memory Read Timing App 20150155017 - Garni; Bradley J. ; et al.	2015-06-04
Integrated circuit having low power mode voltage regulator Grant 8,319,548 - Ramaraju , et al. November 27, 2	2012-11-27
Integrated Circuit Having Low Power Mode Voltage Retulator App 20100207688 - RAMARAJU; RAVINDRARAJ ; et al.	2010-08-19
MRAM architecture with electrically isolated read and write circuitry Grant 7,154,772 - Nahas , et al. December 26, 2	2006-12-26
MRAM sense amplifier having a precharge circuit and method for sensing Grant 7,038,959 - Garni May 2, 2	2006-05-02
Mram Sense Amplifier Having A Precharge Circuit And Method For Sensing App 20060062066 - Garni; Bradley J.	2006-03-23
MRAM architecture with electrically isolated read and write circuitry App 20050152183 - Nahas, Joseph J. ; et al.	2005-07-14
MRAM and methods for reading the MRAM Grant 6,909,631 - Durlam , et al. June 21, 2	2005-06-21
MRAM architecture with electrically isolated read and write circuitry Grant 6,903,964 - Nahas , et al. June 7, 2	2005-06-07
Accelerated life test of MRAM cells Grant 6,894,937 - Garni , et al. May 17, 2	2005-05-17
MRAM architecture Grant 6,888,743 - Durlam , et al. May 3, 2	2005-05-03
Accelerated Life Test Of Mram Cells App 20050068815 - Garni, Bradley J. ; et al.	2005-03-31
Integrated circuit with a transitor over an interconnect layer Grant 6,838,721 - Garni , et al. January 4, 2	2005-01-04
Integrated Circuit With A Transitor Over An Interconnect Layer App 20040211963 - Garni, Bradley J. ; et al.	2004-10-28
Sense amplifier and method for performing a read operation in a MRAM Grant 6,760,266 - Garni , et al. July 6, 2	2004-07-06
MRAM and methods for reading the MRAM App 20040125649 - Durlam, Mark A. ; et al.	2004-07-01
MRAM architecture App 20040125646 - Durlam, Mark A. ; et al.	2004-07-01
Technique For Sensing The State Of A Magneto-resistive Random Access Memory App 20040100845 - Subramanian, Chitra K. ; et al.	2004-05-27
Technique for sensing the state of a magneto-resistive random access memory Grant 6,738,303 - Subramanian , et al. May 18, 2	2004-05-18
Sense amplifier bias circuit for a memory having at least two distinct resistance states Grant 6,700,814 - Nahas , et al. March 2, 2	2004-03-02
Circuit and method for reading a toggle memory cell App 20040008536 - Garni, Bradley J. ; et al.	2004-01-15
Sense amplifier and method for performing a read operation in a MRAM App 20040001383 - Garni, Bradley J. ; et al.	2004-01-01
MRAM architecture with electrically isolated read and write circuitry App 20040001358 - Nahas, Joseph J. ; et al.	2004-01-01
Memory having write current ramp rate control Grant 6,657,889 - Subramanian , et al. December 2, 2	2003-12-02
Sense amplifier incorporating a symmetric midpoint reference Grant 6,621,729 - Garni , et al. September 16, 2	2003-09-16
Sense amplifier for a memory having at least two distinct resistance states Grant 6,600,690 - Nahas , et al. July 29, 2	2003-07-29
Method and circuitry for identifying weak bits in an MRAM Grant 6,538,940 - Nahas , et al. March 25, 2	2003-03-25

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