Garg; Sanjiv

Patent Applications and Registrations

Patent applications and USPTO patent grants for Garg; Sanjiv.The latest application filed is for "risc microprocessor architecture implementing multiple typed register sets".

Company Profile

0.62.38

Garg; Sanjiv - Fremont CA
Garg; Sanjiv - Freemont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
System and method for assigning tags to control instruction processing in a superscalar processor Grant 8,074,052 - Iadonato , et al. December 6, 2	2011-12-06
System and method for handling load and/or store operations in a superscalar microprocessor Grant 8,019,975 - Brashears , et al. September 13, 2	2011-09-13
System and method for register renaming Grant 7,979,678 - Deosaran , et al. July 12, 2	2011-07-12
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor Grant 7,958,337 - Wang , et al. June 7, 2	2011-06-07
RISC microprocessor architecture implementing multiple typed register sets Grant 7,941,636 - Garg , et al. May 10, 2	2011-05-10
High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution Grant 7,941,635 - Nguyen , et al. May 10, 2	2011-05-10
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor Grant 7,934,078 - Wang , et al. April 26, 2	2011-04-26
Superscalar RISC instruction scheduling Grant 7,802,074 - Garg , et al. September 21, 2	2010-09-21
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 7,739,482 - Nguyen , et al. June 15, 2	2010-06-15
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 7,721,070 - Nguyen , et al. May 18, 2	2010-05-18
RISC Microprocessor Architecture Implementing Multiple Typed Register Sets App 20100106942 - GARG; Sanjiv ; et al.	2010-04-29
RISC microprocessor architecture implementing multiple typed register sets Grant 7,685,402 - Garg , et al. March 23, 2	2010-03-23
System and Method for Register Renaming App 20090235053 - Deosaran; Trevor A. ; et al.	2009-09-17
System and method for register renaming Grant 7,558,945 - Deosaran , et al. July 7, 2	2009-07-07
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 7,555,632 - Nguyen , et al. June 30, 2	2009-06-30
RISC microprocessor architecture implementing multiple typed register sets Grant 7,555,631 - Garg , et al. June 30, 2	2009-06-30
System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor App 20090158014 - Wang; Johannes ; et al.	2009-06-18
System and method for handling exceptions and branch mispredictions in a superscalar microprocessor Grant 7,523,296 - Wang , et al. April 21, 2	2009-04-21
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor Grant 7,516,305 - Wang , et al. April 7, 2	2009-04-07
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 7,487,333 - Nguyen , et al. February 3, 2	2009-02-03
High-Performance, Superscalar-Based Computer System with Out-of-Order Instruction Execution App 20090019261 - NGUYEN; Le Trong ; et al.	2009-01-15
System and Method for Assigning Tags to Control Instruction Processing in a Superscalar Processor App 20090013158 - Iadonato; Kevin R. ; et al.	2009-01-08
System and Method for Retiring Approximately Simultaneously a Group of Instructions in a Superscalar Microprocessor App 20090013155 - Wang; Johannes ; et al.	2009-01-08
System and method for assigning tags to control instruction processing in a superscalar processor Grant 7,430,651 - Iadonato , et al. September 30, 2	2008-09-30
Superscalar RISC instruction scheduling App 20080059770 - Garg; Sanjiv ; et al.	2008-03-06
RISC microprocessor architecture implementing multiple typed register sets App 20070113047 - Garg; Sanjiv ; et al.	2007-05-17
High-performance, superscalar-based computer system with out-of-order instruction execution App 20070106878 - Nguyen; Le Trong ; et al.	2007-05-10
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor App 20070106880 - Wang; Johannes ; et al.	2007-05-10
High-performance superscalar-based computer system with out-of order instruction execution and concurrent results distribution App 20070101103 - Nguyen; Le Trong ; et al.	2007-05-03
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 7,162,610 - Nguyen , et al. January 9, 2	2007-01-09
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution App 20060149925 - Nguyen; Le Trong ; et al.	2006-07-06
System and method for assigning tags to control instruction processing in a superscalar processor App 20060123218 - Iadonato; Kevin R. ; et al.	2006-06-08
Superscalar RISC instruction scheduling Grant 7,051,187 - Garg , et al. May 23, 2	2006-05-23
System and method for assigning tags to control instruction processing in a superscalar processor Grant 7,043,624 - Iadonato , et al. May 9, 2	2006-05-09
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 7,028,161 - Nguyen , et al. April 11, 2	2006-04-11
Superscalar RISC instruction scheduling App 20060041736 - Garg; Sanjiv ; et al.	2006-02-23
System and method for register renaming App 20060020773 - Deosaran; Trevor A. ; et al.	2006-01-26
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,986,024 - Nguyen , et al. January 10, 2	2006-01-10
System and method for handling load and/or store operations in a superscalar microprocessor App 20050283591 - Brashears, Cheryl Senter ; et al.	2005-12-22
System and method for register renaming Grant 6,970,995 - Deosaran , et al. November 29, 2	2005-11-29
System and method for handling load and/or store operations in a superscalar microprocessor Grant 6,965,987 - Senter Brashears , et al. November 15, 2	2005-11-15
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,959,375 - Nguyen , et al. October 25, 2	2005-10-25
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor App 20050228973 - Wang, Johannes ; et al.	2005-10-13
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,948,052 - Nguyen , et al. September 20, 2	2005-09-20
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,941,447 - Nguyen , et al. September 6, 2	2005-09-06
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,934,829 - Nguyen , et al. August 23, 2	2005-08-23
System and method for register renaming Grant 6,922,772 - Deosaran , et al. July 26, 2	2005-07-26
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor Grant 6,920,548 - Wang , et al. July 19, 2	2005-07-19
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,915,412 - Nguyen , et al. July 5, 2	2005-07-05
System and method for assigning tags to control instruction processing in a superscalar processor App 20040199746 - Iadonato, Kevin R. ; et al.	2004-10-07
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor App 20040186983 - Wang, Johannes ; et al.	2004-09-23
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor Grant 6,775,761 - Wang , et al. August 10, 2	2004-08-10
System and method for handling load and/or store operations in a superscalar microprocessor App 20040128487 - Brashears, Cheryl Senter ; et al.	2004-07-01
System and method for assigning tags to control instruction processing in a superscalar processor Grant 6,757,808 - Iadonato , et al. June 29, 2	2004-06-29
High performance, superscalar-based computer system with out-of-order instruction execution App 20040093483 - Nguyen, Le Trong ; et al.	2004-05-13
High-performance, superscalar-based computer system with out-of-order instruction execution App 20040093485 - Nguyen, Le Trong ; et al.	2004-05-13
High-performance, superscalar-based computer system with out-of-order instruction execution App 20040093482 - Nguyen, Le-Trong ; et al.	2004-05-13
High-performance, superscalar-based computer system with out-of-order intstruction execution App 20040054872 - Nguyen, Le Trong ; et al.	2004-03-18
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,647,485 - Nguyen , et al. November 11, 2	2003-11-11
RISC microprocessor architecture implementing multiple typed register sets App 20030115440 - Garg, Sanjiv ; et al.	2003-06-19
High-performance, superscalar-based computer system with out-of-order instruction execution App 20030079113 - Nguyen, Le Trong ; et al.	2003-04-24
High-performance, superscalar-based computer system with out-of-order instruction execution App 20030070060 - Nguyen, Le Trong ; et al.	2003-04-10
High-performance, superscalar-based computer system with out-of-order instruction execution App 20030056086 - Nguyen, Le Trong ; et al.	2003-03-20
High-performance, superscalar-based computer system with out-of-order instruction execution App 20030056087 - Nguyen, Le Trong ; et al.	2003-03-20
Superscalar RISC instruction scheduling App 20030005260 - Garg, Sanjiv ; et al.	2003-01-02
System and method for register renaming App 20020194456 - Deosaran, Trevor A. ; et al.	2002-12-19
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor App 20020178347 - Wang, Johannes ; et al.	2002-11-28
System and method for register renaming App 20020083300 - Deosaran, Trevor A. ; et al.	2002-06-27
System and method for assigning tags to control instruction processing in a superscalar processor App 20020053014 - Iadonato, Kevin R. ; et al.	2002-05-02
High-performance, superscalar-based computer system with out-of-order instruction execution App 20020029328 - Nguyen, Le Trong ; et al.	2002-03-07
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution App 20020016903 - Nguyen, Le Trong ; et al.	2002-02-07
RISC microprocessor architecture implementing multiple register sets App 20010034823 - Garg, Sanjiv ; et al.	2001-10-25
Superscalar RISC instruction scheduling Grant 6,289,433 - Garg , et al. September 11, 2	2001-09-11
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 6,282,630 - Nguyen , et al. August 28, 2	2001-08-28
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,272,619 - Nguyen , et al. August 7, 2	2001-08-07
System and method for register renaming App 20010011343 - Deosaran, Trevor A. ; et al.	2001-08-02
High performance, superscalar-based computer system with out-of-order instruction execution Grant 6,256,720 - Nguyen , et al. July 3, 2	2001-07-03
System and method for retiring approximately simultaneously a group of instructions in a superscalar microprocessor Grant 6,131,157 - Wang , et al. October 10, 2	2000-10-10
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 6,128,723 - Nguyen , et al. October 3, 2	2000-10-03
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 6,038,653 - Nguyen , et al. March 14, 2	2000-03-14
High performance, superscalar-based computer system with out-of-order instruction execution Grant 6,038,654 - Nguyen , et al. March 14, 2	2000-03-14
Superscalar RISC instruction scheduling Grant 5,974,526 - Garg , et al. October 26, 1	1999-10-26
System and method for assigning tags to control instruction processing in a superscalar processor Grant 5,896,542 - Iadonato , et al. April 20, 1	1999-04-20
RISC microprocessor architecture implementing multiple typed register sets Grant 5,838,986 - Garg , et al. November 17, 1	1998-11-17
High-performance superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 5,832,292 - Nguyen , et al. November 3, 1	1998-11-03
System and method for retiring instructions in a superscalar microprocessor Grant 5,826,055 - Wang , et al. October 20, 1	1998-10-20
System and method for register renaming Grant 5,809,276 - Deosaran , et al. September 15, 1	1998-09-15
Superscalar risc instruction scheduling Grant 5,737,624 - Garg , et al. April 7, 1	1998-04-07
High-performance superscalar-based computer system with out-of-order instruction execution Grant 5,689,720 - Nguyen , et al. November 18, 1	1997-11-18
RISC microprocessor architecture implementing multiple typed register sets Grant 5,682,546 - Garg , et al. October 28, 1	1997-10-28
System and method for assigning tags to control instruction processing in a superscalar processor Grant 5,628,021 - Iadonato , et al. May 6, 1	1997-05-06
System and method for assigning tags to instructions to control instruction execution Grant 5,604,912 - Iadonato , et al. February 18, 1	1997-02-18
System and method for register renaming Grant 5,590,295 - Deosaran , et al. December 31, 1	1996-12-31
RISC microprocessor architecture implementing multiple typed register sets Grant 5,560,035 - Garg , et al. September 24, 1	1996-09-24
High-performance, superscalar-based computer system with out-of-order instruction execution and concurrent results distribution Grant 5,560,032 - Nguyen , et al. September 24, 1	1996-09-24
High-performance, superscalar-based computer system with out-of-order instruction execution Grant 5,539,911 - Nguyen , et al. July 23, 1	1996-07-23
Superscalar risc instruction scheduling Grant 5,497,499 - Garg , et al. March 5, 1	1996-03-05
RISC microprocessor architecture implementing multiple typed register sets Grant 5,493,687 - Garg , et al. February 20, 1	1996-02-20
RISC microprocessor architecture implementing fast trap and exception state Grant 5,481,685 - Nguyen , et al. January 2, 1	1996-01-02
RISC microprocessor architecture implementing fast trap and exception state Grant 5,448,705 - Nguyen , et al. September 5, 1	1995-09-05