Gardner; Mark

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gardner; Mark.The latest application filed is for "method for threshold voltage tuning through selective deposition of high-k metal gate (hkmg) film stacks".

Company Profile

3.10.9

Gardner; Mark - Cedar Creek TX
Gardner; Mark - Brooklyn NY
Gardner; Mark - Clarence NY
Gardner; Mark - Bakersfield CA
Gardner; Mark - Carlsbad CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Trademarks

Patent Activity

Patent	Date
Method For Threshold Voltage Tuning Through Selective Deposition Of High-k Metal Gate (hkmg) Film Stacks App 20220148924 - SMITH; Jeffrey ; et al.	2022-05-12
Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks Grant 11,264,289 - Smith , et al. March 1, 2	2022-03-01
Method for forming film stacks with multiple planes of transistors having different transistor architectures Grant 11,264,285 - Gardner , et al. March 1, 2	2022-03-01
Display screen with graphical user interface Grant D930,705 - Gardner , et al. September 14, 2	2021-09-14
Display screen with graphical user interface Grant D921,041 - Gardner , et al. June 1, 2	2021-06-01
Device And Method Of Forming With Three-dimensional Memory And Three-dimensional Logic App 20210111258 - Fulford; H. Jim ; et al.	2021-04-15
Method For Threshold Voltage Tuning Through Selective Deposition Of High-k Metal Gate (hkmg) Film Stacks App 20210013111 - SMITH; Jeffrey ; et al.	2021-01-14
Method For Forming Film Stacks With Multiple Planes Of Transistors Having Different Transistor Architectures App 20210013107 - Gardner; Mark ; et al.	2021-01-14
Methods And Systems For Determining Personalized Therapies App 20180107786 - Morrison; Carl ; et al.	2018-04-19
Protective shield for hand-held tools Grant 9,221,166 - Jacobs , et al. December 29, 2	2015-12-29
Methods For Analysis Of Dna Fragments App 20150057182 - MERRIMAN; Barry ; et al.	2015-02-26
Semiconductor device with high-k dielectric layer Grant 7,282,773 - Li , et al. October 16, 2	2007-10-16
Memory device with floating gate stack Grant 7,138,680 - Li , et al. November 21, 2	2006-11-21
Semiconductor device with high-k dielectric layer App 20060125026 - Li; Hong-Jyh ; et al.	2006-06-15
Flash EEPROM with metal floating gate electrode App 20060054943 - Li; Hong-Jyh ; et al.	2006-03-16
Ion implantation of high-k materials in semiconductor devices App 20050202659 - Li, Hong-Jyh ; et al.	2005-09-15
Multilevel transistor formation employing a local substrate formed within a shallow trench Grant 6,150,695 - Gardner , et al. November 21, 2	2000-11-21
Method of forming a semiconductor device having narrow gate electrode Grant 6,096,615 - Gardner , et al. August 1, 2	2000-08-01

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