| Patent | Date |
|---|
Three-dimensional Device With Vertical Core And Bundled Wiring
App 20220293523 - Gardner; Mark I. ; et al. | 2022-09-15 |
3d Device With A Plurality Of Core Wiring Layout Architecture
App 20220293789 - Fulford; H. Jim ; et al. | 2022-09-15 |
High Density Logic Formation Using Multi-dimensional Laser Annealing
App 20220277957 - Fulford; H. Jim ; et al. | 2022-09-01 |
3d Devices With 3d Diffusion Breaks And Method Of Forming The Same
App 20220254690 - FULFORD; H. Jim ; et al. | 2022-08-11 |
Method Of Making Vertical Semiconductor Nanosheets With Diffusion Breaks
App 20220254689 - GARDNER; Mark I. ; et al. | 2022-08-11 |
3d Devices With 3d Diffusion Breaks And Method Of Forming The Same
App 20220254925 - GARDNER; Mark I. ; et al. | 2022-08-11 |
3D semiconductor apparatus manufactured with a cantilever structure and method of manufacture thereof
Grant 11,410,992 - Fulford , et al. August 9, 2 | 2022-08-09 |
Method of making 3D CMOS with integrated channel and S/D regions
Grant 11,410,888 - Gardner , et al. August 9, 2 | 2022-08-09 |
Multiple Nano Layer Transistor Layers With Different Transistor Architectures For Improved Circuit Layout And Performance
App 20220246612 - FULFORD; H. Jim ; et al. | 2022-08-04 |
High Performance 3d Vertical Transistor Device Enhancement Design
App 20220238652 - GARDNER; Mark I. ; et al. | 2022-07-28 |
Localized Stress Regions For Three-dimension Chiplet Formation
App 20220238328 - DEVILLIERS; Anton J. ; et al. | 2022-07-28 |
Localized Stress Regions For Three-dimension Chiplet Formation
App 20220238380 - DEVILLIERS; Anton J. ; et al. | 2022-07-28 |
Method To Enhance 3d Horizontal Nanosheets Device Performance
App 20220238520 - GARDNER; Mark I. ; et al. | 2022-07-28 |
Method of architecture design for enhanced 3D device performance
Grant 11,393,813 - Gardner , et al. July 19, 2 | 2022-07-19 |
Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performance
Grant 11,362,091 - Fulford , et al. June 14, 2 | 2022-06-14 |
High Density Architecture Design For 3d Logic And 3d Memory Circuits
App 20220181315 - Gardner; Mark I. ; et al. | 2022-06-09 |
Method of making six transistor SRAM cell using connections between 3D transistor stacks
Grant 11,342,339 - Gardner , et al. May 24, 2 | 2022-05-24 |
High Density 3d Layout Enhancement Of Multiple Cmos Devices
App 20220140112 - FULFORD; H. Jim ; et al. | 2022-05-05 |
Method For Designing Three Dimensional Metal Lines For Enhanced Device Performance
App 20220139783 - Gardner; Mark I. ; et al. | 2022-05-05 |
High Precision 3d Metal Stacking For A Plurality Of 3d Devices
App 20220139786 - GARDNER; Mark I. ; et al. | 2022-05-05 |
Method Of Making 3d Circuits With Integrated Stacked 3d Metal Lines For High Density Circuits
App 20220115271 - GARDNER; Mark I. ; et al. | 2022-04-14 |
Method for fabricating a 3D semiconductor apparatus having two vertically disposed seminconductor devices
Grant 11,302,587 - Gardner , et al. April 12, 2 | 2022-04-12 |
Plurality Of 3d Vertical Cmos Devices For High Performance Logic
App 20220102345 - GARDNER; Mark I. ; et al. | 2022-03-31 |
High Performance Floating Body Vfet With Dielectric Core
App 20220102552 - FULFORD; H. Jim ; et al. | 2022-03-31 |
Method Of Making A Plurality Of High Density Logic Elements With Advanced Cmos Device Layout
App 20220102533 - GARDNER; Mark I. ; et al. | 2022-03-31 |
Three-dimensional Universal Cmos Device
App 20220102492 - Gardner; Mark I. ; et al. | 2022-03-31 |
High density architecture design for 3D logic and 3D memory circuits
Grant 11,282,828 - Gardner , et al. March 22, 2 | 2022-03-22 |
Device and method of forming with three-dimensional memory and three-dimensional logic
Grant 11,276,704 - Gardner , et al. March 15, 2 | 2022-03-15 |
Method For Fabricating A 3d Semiconductor Apparatus Having Two Vertically Disposed Seminconductor Devices
App 20220077003 - GARDNER; Mark I. ; et al. | 2022-03-10 |
Optimum High Density 3d Device Layout And Method Of Fabrication
App 20220059413 - GARDNER; Mark I. ; et al. | 2022-02-24 |
Multiple Planes Of Transistors With Different Transistor Architectures To Enhance 3d Logic And Memory Circuits
App 20220052186 - GARDNER; Mark I. ; et al. | 2022-02-17 |
Formation Of Low-temperature And High-temperature In-situ Doped Source And Drain Epitaxy Using Selective Heating For Wrap-around Contact And Vertically Stacked Device Architectures
App 20220051905 - SMITH; Jeffrey ; et al. | 2022-02-17 |
High performance CMOS using 3D device layout
Grant 11,251,159 - Fulford , et al. February 15, 2 | 2022-02-15 |
Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits
Grant 11,251,080 - Gardner , et al. February 15, 2 | 2022-02-15 |
High Performance Nanosheet Fabrication Method With Enhanced High Mobility Channel Elements
App 20220020744 - Gardner; Mark I. ; et al. | 2022-01-20 |
Multiple planes of transistors with different transistor architectures to enhance 3D logic and memory circuits
Grant 11,222,964 - Gardner , et al. January 11, 2 | 2022-01-11 |
3d Semiconductor Apparatus Manufactured With A Cantilever Structure And Method Of Manufacture Thereof
App 20220005805 - FULFORD; H. Jim ; et al. | 2022-01-06 |
Method Of Making 3d Isolation
App 20210391207 - GARDNER; Mark I. ; et al. | 2021-12-16 |
High performance nanosheet fabrication method with enhanced high mobility channel elements
Grant 11,195,832 - Gardner , et al. December 7, 2 | 2021-12-07 |
Method Of Architecture Design For Enhanced 3d Device Performance
App 20210366904 - GARDNER; Mark I. ; et al. | 2021-11-25 |
Metal Connections And Routing For Advanced 3d Layout Designs
App 20210366787 - FULFORD; H. Jim ; et al. | 2021-11-25 |
Method for fabrication of high density logic and memory for advanced circuit architecture
Grant 11,177,250 - Gardner , et al. November 16, 2 | 2021-11-16 |
Method Of Making Multiple Nano Layer Transistors To Enhance A Multiple Stack Cfet Performance
App 20210351180 - Fulford; H. Jim ; et al. | 2021-11-11 |
High performance circuit applications using stacked 3D metal lines
Grant 11,171,208 - Fulford , et al. November 9, 2 | 2021-11-09 |
High Performance Multi-dimensional Device And Logic Integration
App 20210343714 - GARDNER; Mark I. ; et al. | 2021-11-04 |
Method Of Expanding 3d Device Architectural Designs For Enhanced Performance
App 20210343857 - GARDNER; Mark I. ; et al. | 2021-11-04 |
Unified Architectural Design For Enhanced 3d Circuit Options
App 20210313327 - GARDNER; Mark I. ; et al. | 2021-10-07 |
Method of making 3D source drains with hybrid stacking for optimum 3D logic layout
Grant 11,139,213 - Gardner , et al. October 5, 2 | 2021-10-05 |
Method of making multiple nano layer transistors to enhance a multiple stack CFET performance
Grant 11,133,310 - Fulford , et al. September 28, 2 | 2021-09-28 |
Horizontal Programmable Conducting Bridges Between Conductive Lines
App 20210287980 - Fulford; H. Jim ; et al. | 2021-09-16 |
High density logic formation using multi-dimensional laser annealing
Grant 11,114,346 - Fulford , et al. September 7, 2 | 2021-09-07 |
Multi-dimensional planes of logic and memory formation using single crystal silicon orientations
Grant 11,107,733 - Gardner , et al. August 31, 2 | 2021-08-31 |
High Density Architecture Design For 3d Logic And 3d Memory Circuits
App 20210265333 - Gardner; Mark I. ; et al. | 2021-08-26 |
Architecture Design And Process For 3d Logic And 3d Memory
App 20210249430 - Fulford; H. Jim ; et al. | 2021-08-12 |
Efficient Three-dimensional Design For Logic Applications Using Variable Voltage Threshold Three-dimensional Cmos Devices
App 20210242351 - GARDNER; MARK I. ; et al. | 2021-08-05 |
Horizontal programmable conducting bridges between conductive lines
Grant 11,069,616 - Fulford , et al. July 20, 2 | 2021-07-20 |
Method Of Making A Continuous Channel Between 3d Cmos
App 20210217666 - FULFORD; H. Jim ; et al. | 2021-07-15 |
Method Of Making Six Transistor Sram Cell Using Connections Between 3d Transistor Stacks
App 20210202499 - GARDNER; Mark I. ; et al. | 2021-07-01 |
3d Complementary Metal Oxide Semiconductor (cmos) Device And Method Of Forming The Same
App 20210202481 - FULFORD; H. Jim ; et al. | 2021-07-01 |
Method Of Making 3d Cmos With Integrated Channel And S/d Regions
App 20210175128 - GARDNER; Mark I. ; et al. | 2021-06-10 |
3d Semiconductor Apparatus Manufactured With A Plurality Of Substrates And Method Of Manufacture Thereof
App 20210175358 - GARDNER; Mark I. ; et al. | 2021-06-10 |
High Performance Circuit Applications Using Stacked 3d Metal Lines
App 20210175327 - FULFORD; H. Jim ; et al. | 2021-06-10 |
High Performance Cmos Using 3d Device Layout
App 20210175209 - FULFORD; H. Jim ; et al. | 2021-06-10 |
Method Of Making 3d Circuits With Integrated Stacked 3d Metal Lines For High Density Circuits
App 20210166975 - GARDNER; Mark I. ; et al. | 2021-06-03 |
Method Of Making 3d Source Drains With Hybrid Stacking For Optimum 3d Logic Layout
App 20210143065 - GARDNER; Mark I. ; et al. | 2021-05-13 |
Method Of Making A Charge Trap Tfet Semiconductor Device For Advanced Logic Operations
App 20210118879 - GARDNER; Mark I. ; et al. | 2021-04-22 |
Device And Method Of Forming With Three-dimensional Memory And Three-dimensional Logic
App 20210111183 - Gardner; Mark I. ; et al. | 2021-04-15 |
Method Of Making Multiple Nano Layer Transistors To Enhance A Multiple Stack Cfet Performance
App 20210104523 - Fulford; H. Jim ; et al. | 2021-04-08 |
High Performance Nanosheet Fabrication Method With Enhanced High Mobility Channel Elements
App 20210104522 - Gardner; Mark I. ; et al. | 2021-04-08 |
Method For Fabrication Of High Density Logic And Memory For Advanced Circuit Architecture
App 20210082901 - GARDNER; Mark I. ; et al. | 2021-03-18 |
Multi-dimensional Planes Of Logic And Memory Formation Using Single Crystal Silicon Orientations
App 20210043516 - GARDNER; Mark I. ; et al. | 2021-02-11 |
High Density Logic Formation Using Multi-dimensional Laser Annealing
App 20210043519 - FULFORD; H. Jim ; et al. | 2021-02-11 |
Multiple Planes Of Transistors With Different Transistor Architectures To Enhance 3d Logic And Memory Circuits
App 20210013326 - Gardner; Mark I. ; et al. | 2021-01-14 |
Multiple Nano Layer Transistor Layers With Different Transistor Architectures For Improved Circuit Layout And Performance
App 20200411518 - FULFORD; H. Jim ; et al. | 2020-12-31 |
Programmable Connection Segment And Method Of Forming The Same
App 20200365511 - Gardner; Mark I. ; et al. | 2020-11-19 |
Horizontal Programmable Conducting Bridges Between Conductive Lines
App 20200365507 - Fulford; H. Jim ; et al. | 2020-11-19 |
Multi-dimensional Vertical Switching Connections For Connecting Circuit Elements
App 20200365506 - Gardner; Mark I. ; et al. | 2020-11-19 |
Method of making a plurality of protected devices in communication with a background device
Grant 7,832,649 - Gardner , et al. November 16, 2 | 2010-11-16 |
Method of Making a Plurality of Protected Devices in Communication with a Background Device
App 20090145970 - Gardner; Mark I. ; et al. | 2009-06-11 |
Devices for an insulated dielectric interface between high-k material and silicon
App 20060115937 - Barnett; Joel M. ; et al. | 2006-06-01 |
Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites
Grant 6,979,878 - Gardner , et al. December 27, 2 | 2005-12-27 |
Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance
Grant 6,911,707 - Gardner , et al. June 28, 2 | 2005-06-28 |
Methods and devices for an insulated dielectric interface between high-k material and silicon
App 20050070120 - Barnett, Joel M. ; et al. | 2005-03-31 |
Method of making ultra thin oxide formation using selective etchback technique integrated with thin nitride layer for high performance MOSFET
Grant 6,767,794 - Gardner , et al. July 27, 2 | 2004-07-27 |
High performance MOSFET with modulated channel gate thickness
Grant 6,743,688 - Gardner , et al. June 1, 2 | 2004-06-01 |
Method of making enhanced trench oxide with low temperature nitrogen integration
Grant 6,727,569 - Gardner , et al. April 27, 2 | 2004-04-27 |
Semiconductor structure having elevated salicided source/drain regions and metal gate electrode on nitride/oxide dielectric
Grant 6,674,135 - Cheek , et al. January 6, 2 | 2004-01-06 |
Integrated circuit with differing gate oxide thickness
Grant 6,661,061 - Gardner , et al. December 9, 2 | 2003-12-09 |
Tri-level segmented control transistor and fabrication method
Grant 6,661,057 - Dawson , et al. December 9, 2 | 2003-12-09 |
Semiconductor structure having a metal gate electrode and elevated salicided source/drain regions and a method for manufacture
Grant 6,638,829 - Cheek , et al. October 28, 2 | 2003-10-28 |
Semiconductor device having large-area silicide layer and process of fabrication thereof
Grant 6,603,180 - Gardner , et al. August 5, 2 | 2003-08-05 |
Photolithographic system including light filter that compensates for lens error
Grant 6,552,776 - Wristers , et al. April 22, 2 | 2003-04-22 |
Ultrathin High-k Gate Dielectric With Favorable Interface Properties For Improved Semiconductor Device Performance
App 20030057432 - GARDNER, MARK I. ; et al. | 2003-03-27 |
Asymmetrical N-channel and P-channel devices
Grant 6,504,218 - Kadosh , et al. January 7, 2 | 2003-01-07 |
Asymmetrical transistor having a barrier-incorporated gate oxide and a graded implant only in the drain-side junction area
Grant 6,483,157 - Gardner , et al. November 19, 2 | 2002-11-19 |
Method of making high performance transistor with a reduced width gate electrode and device comprising same
Grant 6,429,052 - Gardner , et al. August 6, 2 | 2002-08-06 |
Elevated transistor fabrication technique
Grant 6,420,730 - Gardner , et al. July 16, 2 | 2002-07-16 |
Transistor having enhanced metal silicide and a self-aligned gate electrode
Grant 6,410,967 - Hause , et al. June 25, 2 | 2002-06-25 |
In-situ stack for high volume production of isolation regions
Grant 6,383,874 - Sun , et al. May 7, 2 | 2002-05-07 |
Dopant diffusion-retarding barrier region formed within polysilicon gate layer
Grant 6,380,055 - Gardner , et al. April 30, 2 | 2002-04-30 |
Nitrogenated gate structure for improved transistor performance and method for making same
Grant 6,373,113 - Gardner , et al. April 16, 2 | 2002-04-16 |
Semiconductor topography having improved active device isolation and reduced dopant migration
Grant 6,362,510 - Gardner , et al. March 26, 2 | 2002-03-26 |
Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation
Grant 6,355,955 - Gardner , et al. March 12, 2 | 2002-03-12 |
Method Of Making Ultra Thin Oxide Formation Using Selective Etchback Technique Integrated With Thin Nitride Layer For High Performance Mosfet
App 20020022325 - GARDNER, MARK I. ; et al. | 2002-02-21 |
Igfet With Silicide Contact On Ultra-thin Gate
App 20020003273 - DAWSON, ROBERT ; et al. | 2002-01-10 |
Dopant Diffusion-retarding Barrier Region Formed Within Polysilicon Gate Layer
App 20020004294 - GARDNER, MARK I. ; et al. | 2002-01-10 |
Ultra Short Channel Length Dictated By The Width Of A Sacrificial Sidewall Spacer
App 20020003272 - GARDNER, MARK I. ; et al. | 2002-01-10 |
Ultrathin, nitrogen-containing MOSFET sidewall spacers using low-temperature semiconductor fabrication process
Grant 6,323,519 - Gardner , et al. November 27, 2 | 2001-11-27 |
Spacer formation for precise salicide formation
Grant 6,323,561 - Gardner , et al. November 27, 2 | 2001-11-27 |
Method Of Making An Igfet Using Solid Phase Diffusion To Dope The Gate, Source And Drain
App 20010039094 - WRISTERS, DERICK J. ; et al. | 2001-11-08 |
Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures
Grant 6,303,962 - Gardner , et al. October 16, 2 | 2001-10-16 |
Transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection
Grant 6,297,535 - Gardner , et al. October 2, 2 | 2001-10-02 |
Transistor Having A Transition Metal Oxide Gate Dielectric And Method Of Making Same
App 20010020723 - GARDNER, MARK I. ; et al. | 2001-09-13 |
High Density Memory Cell Assembly And Methods
App 20010020716 - GARDNER, MARK I. ; et al. | 2001-09-13 |
Method of making air gap isolation by making a lateral EPI bridge for low K isolation advanced CMOS fabrication
Grant 6,268,637 - Gardner , et al. July 31, 2 | 2001-07-31 |
Metal silicide transistor gate spaced from a semiconductor substrate by a ceramic gate dielectric having a high dielectric constant
Grant 6,265,749 - Gardner , et al. July 24, 2 | 2001-07-24 |
Buried local interconnect
Grant 6,261,908 - Hause , et al. July 17, 2 | 2001-07-17 |
Semiconductor device having ultra shallow junctions and a reduced channel length and method for making same
Grant 6,261,909 - Gardner , et al. July 17, 2 | 2001-07-17 |
Multiple split gate semiconductor device and fabrication method
Grant 6,259,142 - Dawson , et al. July 10, 2 | 2001-07-10 |
Ultra-thin gate oxide formation using an N2O plasma
Grant 6,258,730 - Sun , et al. July 10, 2 | 2001-07-10 |
Integrated circuit gate conductor which uses layered spacers to produce a graded junction
Grant 6,258,680 - Fulford, Jr. , et al. July 10, 2 | 2001-07-10 |
Ultra high density NOR gate using a stacked transistor arrangement
Grant 6,259,118 - Kadosh , et al. July 10, 2 | 2001-07-10 |
High K gate electrode
Grant 6,258,675 - Gardner , et al. July 10, 2 | 2001-07-10 |
Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit
Grant 6,255,698 - Gardner , et al. July 3, 2 | 2001-07-03 |
CMOS transistor design for shared N+/P+ electrode with enhanced device performance
Grant 6,252,283 - Gardner , et al. June 26, 2 | 2001-06-26 |
Ultrathin deposited gate dielectric formation using low-power, low-pressure PECVD for improved semiconductor device performance
Grant 6,251,800 - Sun , et al. June 26, 2 | 2001-06-26 |
Method of forming ultra thin gate dielectric for high performance semiconductor devices
Grant 6,245,652 - Gardner , et al. June 12, 2 | 2001-06-12 |
Nitrogenated Trench Liner For Improved Shallow Trench Isolation
App 20010001723 - GARDNER, MARK I. ; et al. | 2001-05-24 |
Semiconductor fabrication having multi-level transistors and high density interconnect therebetween
Grant 6,232,637 - Gardner , et al. May 15, 2 | 2001-05-15 |
Integrated circuit incorporating a memory cell and a transistor elevated above an insulating base
Grant 6,225,646 - Gardner , et al. May 1, 2 | 2001-05-01 |
Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion
Grant 6,225,151 - Gardner , et al. May 1, 2 | 2001-05-01 |
Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof
Grant 6,225,168 - Gardner , et al. May 1, 2 | 2001-05-01 |
Ultra short transistor channel length dictated by the width of a sidewall spacer
Grant 6,225,201 - Gardner , et al. May 1, 2 | 2001-05-01 |
Salicide and gate dielectric formed from a single layer of refractory metal
Grant 6,222,240 - Gardner , et al. April 24, 2 | 2001-04-24 |
Method of making elevated source/drain using poly underlayer
Grant 6,211,025 - Gardner , et al. April 3, 2 | 2001-04-03 |
High K integration of gate dielectric with integrated spacer formation for high speed CMOS
Grant 6,207,995 - Gardner , et al. March 27, 2 | 2001-03-27 |
Integration of high K spacers for dual gate oxide channel fabrication technique
Grant 6,207,485 - Gardner , et al. March 27, 2 | 2001-03-27 |
Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device
Grant 6,204,153 - Gardner , et al. March 20, 2 | 2001-03-20 |
Mask for asymmetrical transistor formation with paired transistors
Grant 6,200,862 - Gardner , et al. March 13, 2 | 2001-03-13 |
Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate
Grant 6,200,865 - Gardner , et al. March 13, 2 | 2001-03-13 |
Trench transistor with insulative spacers
Grant 6,201,278 - Gardner , et al. March 13, 2 | 2001-03-13 |
Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls
Grant 6,197,645 - Michael , et al. March 6, 2 | 2001-03-06 |
Ferroelectric-enhanced tantalum pentoxide for dielectric material applications in CMOS devices
Grant 6,197,668 - Gardner , et al. March 6, 2 | 2001-03-06 |
High density trench fill due to new spacer fill method including isotropically etching silicon nitride spacers
Grant 6,194,283 - Gardner , et al. February 27, 2 | 2001-02-27 |
Formation and control of a vertically oriented transistor channel length
Grant 6,191,446 - Gardner , et al. February 20, 2 | 2001-02-20 |
Method of forming an insulated-gate field-effect transistor with metal spacers
Grant 6,188,114 - Gardner , et al. February 13, 2 | 2001-02-13 |
High performance transistor fabricated on a dielectric film and method of making same
Grant 6,188,107 - Gardner , et al. February 13, 2 | 2001-02-13 |
Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions
Grant 6,187,620 - Fulford, Jr. , et al. February 13, 2 | 2001-02-13 |
Method and structure for isolating semiconductor devices after transistor formation
Grant 6,184,566 - Gardner , et al. February 6, 2 | 2001-02-06 |
Method of making high performance MOSFET with channel scaling mask feature
Grant 6,180,465 - Gardner , et al. January 30, 2 | 2001-01-30 |
Method of making high performance MOSFET with polished gate and source/drain feature
Grant 6,174,794 - Gardner , et al. January 16, 2 | 2001-01-16 |
Source/drain junction areas self aligned between a sidewall spacer and an etched lateral sidewall
Grant 6,172,381 - Gardner , et al. January 9, 2 | 2001-01-09 |
Semiconductor devices comprised of one or more epitaxial layers
Grant 6,169,306 - Gardner , et al. January 2, 2 | 2001-01-02 |
Apparatus for performing jet vapor reduction of the thickness of process layers
Grant 6,165,314 - Gardner , et al. December 26, 2 | 2000-12-26 |
Enhanced silicidation formation for high speed MOS device by junction grading with dual implant dopant species
Grant 6,165,858 - Gardner , et al. December 26, 2 | 2000-12-26 |
Semiconductor device with a composite gate dielectric layer and gate barrier layer and method of making same
Grant 6,163,060 - Gardner , et al. December 19, 2 | 2000-12-19 |
Method of fabricating a transistor with a dielectric underlayer and device incorporating same
Grant 6,162,688 - Gardner , et al. December 19, 2 | 2000-12-19 |
Method of forming a metal gate electrode using replaced polysilicon structure
Grant 6,162,694 - Cheek , et al. December 19, 2 | 2000-12-19 |
Multi-layer gate conductor having a diffusion barrier in the bottom layer
Grant 6,160,300 - Gardner , et al. December 12, 2 | 2000-12-12 |
Integrated circuit utilizing an air gap to reduce capacitance between adjacent metal linewidths
Grant 6,160,316 - Gardner , et al. December 12, 2 | 2000-12-12 |
Method and system for heating semiconductor wafers
Grant 6,152,075 - Gardner , et al. November 28, 2 | 2000-11-28 |
Ultra short transistor channel length formed using a gate dielectric having a relatively high dielectric constant
Grant 6,153,477 - Gardner , et al. November 28, 2 | 2000-11-28 |
Method of making a high performance transistor with elevated spacer formation and self-aligned channel regions
Grant 6,150,222 - Gardner , et al. November 21, 2 | 2000-11-21 |
Method of making an ultra thin silicon nitride film
Grant 6,150,286 - Sun , et al. November 21, 2 | 2000-11-21 |
Method and apparatus for in-situ cleaning of polysilicon-coated quartz furnaces
Grant 6,148,832 - Gilmer , et al. November 21, 2 | 2000-11-21 |
Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof
Grant 6,146,934 - Gardner , et al. November 14, 2 | 2000-11-14 |
Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance
Grant 6,146,978 - Michael , et al. November 14, 2 | 2000-11-14 |
Ultrathin silicon nitride containing sidewall spacers for improved transistor performance
Grant 6,144,071 - Gardner , et al. November 7, 2 | 2000-11-07 |
Semiconductor device with self-aligned metal-containing gate
Grant 6,140,688 - Gardner , et al. October 31, 2 | 2000-10-31 |
Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate
Grant 6,140,691 - Gardner , et al. October 31, 2 | 2000-10-31 |
Method of making high performance MOSFET with integrated simultaneous formation of source/drain and gate regions
Grant 6,140,191 - Gardner , et al. October 31, 2 | 2000-10-31 |
Method of reducing via and contact dimensions beyond photolithography equipment limits
Grant 6,137,182 - Hause , et al. October 24, 2 | 2000-10-24 |
Gate conductor formed within a trench bounded by slanted sidewalls
Grant 6,130,454 - Gardner , et al. October 10, 2 | 2000-10-10 |
Ultra shallow extension formation using disposable spacers
Grant 6,127,234 - Gardner , et al. October 3, 2 | 2000-10-03 |
Incorporating barrier atoms into a gate dielectric using gas cluster ion beam implantation
Grant 6,124,620 - Gardner , et al. September 26, 2 | 2000-09-26 |
Semiconductor device having a group of high performance transistors and method of manufacture thereof
Grant 6,121,643 - Gardner , et al. September 19, 2 | 2000-09-19 |
Method of making a semiconductor device with a multi-level gate structure
Grant 6,121,094 - Gardner , et al. September 19, 2 | 2000-09-19 |
Selective spacer formation for optimized silicon area reduction
Grant 6,121,099 - Fulford, Jr. , et al. September 19, 2 | 2000-09-19 |
Semiconductor device with layered doped regions and methods of manufacture
Grant 6,117,739 - Gardner , et al. September 12, 2 | 2000-09-12 |
Transistor with integrated poly/metal gate electrode
Grant 6,118,163 - Gardner , et al. September 12, 2 | 2000-09-12 |
Test structure responsive to electrical signals for determining lithographic misalignment of conductors relative to vias
Grant 6,118,137 - Fulford, Jr. , et al. September 12, 2 | 2000-09-12 |
Method of making a semiconductor device with a composite gate dielectric layer and gate barrier layer
Grant 6,114,228 - Gardner , et al. September 5, 2 | 2000-09-05 |
Semiconductor device having elevated gate electrode and elevated active regions and method of manufacture thereof
Grant 6,110,786 - Gardner , et al. August 29, 2 | 2000-08-29 |
Method of integration of nitrogen bearing high K film
Grant 6,110,784 - Gardner , et al. August 29, 2 | 2000-08-29 |
Semiconductor fabrication employing self-aligned sidewall spacers laterally adjacent to a transistor gate
Grant 6,111,292 - Gardner , et al. August 29, 2 | 2000-08-29 |
CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions
Grant 6,107,130 - Fulford, Jr. , et al. August 22, 2 | 2000-08-22 |
Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance
Grant 6,107,129 - Gardner , et al. August 22, 2 | 2000-08-22 |
Multiple spacer formation/removal technique for forming a graded junction
Grant 6,104,063 - Fulford, Jr. , et al. August 15, 2 | 2000-08-15 |
Semiconductor device having an elevated active region formed in an oxide trench
Grant 6,104,069 - Duane , et al. August 15, 2 | 2000-08-15 |
Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication
Grant 6,103,559 - Gardner , et al. August 15, 2 | 2000-08-15 |
Semiconductor device having gate electrode with a sidewall air gap
Grant 6,104,077 - Gardner , et al. August 15, 2 | 2000-08-15 |
Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
Grant 6,100,173 - Gardner , et al. August 8, 2 | 2000-08-08 |
Method of making ultra thin gate oxide using aluminum oxide
Grant 6,100,204 - Gardner , et al. August 8, 2 | 2000-08-08 |
Method of forming trench transistor with insulative spacers
Grant 6,100,146 - Gardner , et al. August 8, 2 | 2000-08-08 |
Manufacturing process for reducing feature dimensions in a semiconductor
Grant 6,096,659 - Gardner , et al. August 1, 2 | 2000-08-01 |
Metal attachment method and structure for attaching substrates at low temperatures
Grant 6,097,096 - Gardner , et al. August 1, 2 | 2000-08-01 |
Method of making an IGFET and a protected resistor with reduced processing steps
Grant 6,096,591 - Gardner , et al. August 1, 2 | 2000-08-01 |
Oxide liner for high reliability with reduced encroachment of the source/drain region
Grant 6,093,611 - Gardner , et al. July 25, 2 | 2000-07-25 |
Process for making high performance MOSFET with scaled gate electrode thickness
Grant 6,090,676 - Gardner , et al. July 18, 2 | 2000-07-18 |
Transistor fabrication process employing a common chamber for gate oxide and gate conductor formation
Grant 6,087,249 - Gardner , et al. July 11, 2 | 2000-07-11 |
Trench isolation structure partially bound between a pair of low K dielectric structures
Grant 6,087,705 - Gardner , et al. July 11, 2 | 2000-07-11 |
Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls
Grant 6,087,706 - Dawson , et al. July 11, 2 | 2000-07-11 |
Semiconductor wafer, handling apparatus, and method
Grant 6,086,976 - Gardner , et al. July 11, 2 | 2000-07-11 |
Transistor having a metal silicide self-aligned to the gate
Grant 6,084,280 - Gardner , et al. July 4, 2 | 2000-07-04 |
Metal attachment method and structure for attaching substrates at low temperatures
Grant 6,080,640 - Gardner , et al. June 27, 2 | 2000-06-27 |
Advanced trench isolation fabrication scheme for precision polysilicon gate control
Grant 6,077,748 - Gardner , et al. June 20, 2 | 2000-06-20 |
V-gate transistor
Grant 6,078,078 - Gardner , et al. June 20, 2 | 2000-06-20 |
Asymmetrical transistor with lightly and heavily doped drain regions and ultra-heavily doped source region
Grant 6,078,080 - Kadosh , et al. June 20, 2 | 2000-06-20 |
Method of forming an ultrathin gate dielectric
Grant 6,074,919 - Gardner , et al. June 13, 2 | 2000-06-13 |
Method and structure for isolating semiconductor devices after transistor formation
Grant 6,074,904 - Spikes, Jr. , et al. June 13, 2 | 2000-06-13 |
Elevated transistor fabrication technique
Grant 6,075,258 - Gardner , et al. June 13, 2 | 2000-06-13 |
Ultra high density inverter using a stacked transistor arrangement
Grant 6,075,268 - Gardner , et al. June 13, 2 | 2000-06-13 |
Transistor having an etchant-scalable channel length and method of making same
Grant 6,072,213 - Gardner , et al. June 6, 2 | 2000-06-06 |
Lightly doped drain formation integrated with source/drain formation for high-performance transistor formation
Grant 6,069,387 - Gardner May 30, 2 | 2000-05-30 |
Transistor fabrication employing implantation of dopant into junctions without subjecting sidewall surfaces of a gate conductor to ion bombardment
Grant 6,069,046 - Gardner , et al. May 30, 2 | 2000-05-30 |
Integrated circuit including vertical transistors with spacer gates having selected gate widths
Grant 6,069,384 - Hause , et al. May 30, 2 | 2000-05-30 |
Semiconductor device having gate electrodes with different gate insulators and fabrication thereof
Grant 6,064,102 - Gardner , et al. May 16, 2 | 2000-05-16 |
Method of making NMOS and PMOS devices with reduced masking steps
Grant 6,060,345 - Hause , et al. May 9, 2 | 2000-05-09 |
Semiconductor device having a tri-layer gate insulating dielectric
Grant 6,057,584 - Gardner , et al. May 2, 2 | 2000-05-02 |
Semiconductor device having a nitrogen bearing isolation region
Grant 6,057,209 - Gardner , et al. May 2, 2 | 2000-05-02 |
Method of scaling dielectric thickness in a semiconductor process with ion implantation
Grant 6,054,374 - Gardner , et al. April 25, 2 | 2000-04-25 |
Elevated local interconnect and contact structure
Grant 6,054,385 - Gardner , et al. April 25, 2 | 2000-04-25 |
Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode
Grant 6,051,487 - Gardner , et al. April 18, 2 | 2000-04-18 |
Method of making N-channel and P-channel IGFETs using selective doping and activation for the N-channel gate
Grant 6,051,459 - Gardner , et al. April 18, 2 | 2000-04-18 |
Transistor gate conductor having sidewall surfaces upon which a spacer having a profile that substantially prevents silicide bridging is formed
Grant 6,051,863 - Hause , et al. April 18, 2 | 2000-04-18 |
Method and structure for replaceable gate electrode in insulated gate field effect transistors
Grant 6,051,486 - Gardner April 18, 2 | 2000-04-18 |
Transistor having a barrier layer below a high permittivity gate dielectric
Grant 6,051,865 - Gardner , et al. April 18, 2 | 2000-04-18 |
Flash memory device having high permittivity stacked dielectric and fabrication thereof
Grant 6,048,766 - Gardner , et al. April 11, 2 | 2000-04-11 |
Selectively sized spacers
Grant 6,046,089 - Gardner , et al. April 4, 2 | 2000-04-04 |
Semiconductor device having dual gate electrode material and process of fabrication thereof
Grant 6,043,157 - Gardner , et al. March 28, 2 | 2000-03-28 |
Oxide formation technique using thin film silicon deposition
Grant 6,040,207 - Gardner , et al. March 21, 2 | 2000-03-21 |
Asymmetrical transistor formed from a gate conductor of unequal thickness
Grant 6,040,220 - Gardner , et al. March 21, 2 | 2000-03-21 |
Dual gate oxide thickness integrated circuit and process for making same
Grant 6,033,943 - Gardner March 7, 2 | 2000-03-07 |
Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device
Grant 6,030,752 - Fulford, Jr. , et al. February 29, 2 | 2000-02-29 |
Method of making an IGFET with a selectively doped gate in combination with a protected resistor
Grant 6,027,964 - Gardner , et al. February 22, 2 | 2000-02-22 |
Method of making an IGFET with a non-uniform lateral doping profile in the channel region
Grant 6,027,978 - Gardner , et al. February 22, 2 | 2000-02-22 |
Multi-level transistor fabrication method having an inverted, upper level transistor which shares a gate conductor with a non-inverted, lower level transistor
Grant 6,025,633 - Kadosh , et al. February 15, 2 | 2000-02-15 |
Method of fabricating a semiconductor device having nitrogen-bearing gate electrode
Grant 6,020,260 - Gardner February 1, 2 | 2000-02-01 |
Transistors having a scaled channel length and integrated spacers with enhanced silicidation properties
Grant 6,018,179 - Gardner , et al. January 25, 2 | 2000-01-25 |
Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant
Grant 6,015,739 - Gardner , et al. January 18, 2 | 2000-01-18 |
Semiconductor device having a PMOS device with a source/drain region formed using a heavy atom p-type implant and method of manufacture thereof
Grant 6,013,546 - Gardner , et al. January 11, 2 | 2000-01-11 |
Short channel length MOSFET transistor
Grant 6,011,290 - Gardner , et al. January 4, 2 | 2000-01-04 |
Trench isolation structure having a low K dielectric encapsulated by oxide
Grant 6,008,109 - Fulford, Jr. , et al. December 28, 1 | 1999-12-28 |
Process for formation of isolation trenches with high-K gate dielectrics
Grant 6,008,095 - Gardner , et al. December 28, 1 | 1999-12-28 |
Ultra short transistor fabrication method
Grant 6,008,096 - Gardner , et al. December 28, 1 | 1999-12-28 |
Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device
Grant 6,005,285 - Gardner , et al. December 21, 1 | 1999-12-21 |
Trench transistor with source contact in trench
Grant 6,005,272 - Gardner , et al. December 21, 1 | 1999-12-21 |
Semiconductor device with a multi-level gate structure and a gate dielectric composed of barium zirconium titanate material
Grant 6,005,274 - Gardner , et al. December 21, 1 | 1999-12-21 |
Compound material T gate structure for devices with gate dielectrics having a high dielectric constant
Grant 6,002,150 - Gardner , et al. December 14, 1 | 1999-12-14 |
Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate
Grant 5,998,288 - Gardner , et al. December 7, 1 | 1999-12-07 |
Method of making high performance MOSFET with integrated poly/metal gate electrode
Grant 5,994,193 - Gardner , et al. November 30, 1 | 1999-11-30 |
Diamond etch stop rendered conductive by a gas cluster ion beam implant of titanium
Grant 5,990,493 - Gardner , et al. November 23, 1 | 1999-11-23 |
Semiconductor arrangement with lightly doped regions under a gate structure
Grant 5,990,532 - Gardner November 23, 1 | 1999-11-23 |
Transistor with ultra short length defined partially by sidewall oxidation of a gate conductor overlying the channel length
Grant 5,989,967 - Gardner , et al. November 23, 1 | 1999-11-23 |
Polishing method for thin gates dielectric in semiconductor process
Grant 5,985,706 - Gilmer , et al. November 16, 1 | 1999-11-16 |
Method for forming asymmetrical p-channel transistor having nitrided oxide patterned to selectively form a sidewall spacer
Grant 5,985,724 - Kadosh , et al. November 16, 1 | 1999-11-16 |
Test structure for determining how lithographic patterning of a gate conductor affects transistor properties
Grant 5,986,283 - Bush , et al. November 16, 1 | 1999-11-16 |
Method and apparatus for high performance transistor devices
Grant 5,981,363 - Gardner , et al. November 9, 1 | 1999-11-09 |
Stacked poly-oxide-poly gate for improved silicide formation
Grant 5,981,365 - Cheek , et al. November 9, 1 | 1999-11-09 |
Method of making a self-aligned disposable gate electrode for advanced CMOS design
Grant 5,976,924 - Gardner , et al. November 2, 1 | 1999-11-02 |
Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device
Grant 5,976,956 - Gardner , et al. November 2, 1 | 1999-11-02 |
Implanted isolation structure formation for high density CMOS integrated circuits
Grant 5,976,952 - Gardner , et al. November 2, 1 | 1999-11-02 |
MOSFET device with an amorphized source
Grant 5,969,407 - Gardner , et al. October 19, 1 | 1999-10-19 |
Method and structure for high aspect gate and short channel length insulated gate field effect transistors
Grant 5,969,394 - Gardner , et al. October 19, 1 | 1999-10-19 |
Method of making a plug transistor
Grant 5,970,331 - Gardner , et al. October 19, 1 | 1999-10-19 |
Semiconductor device having nitrogen enhanced high permittivity gate insulating layer and fabrication thereof
Grant 5,963,810 - Gardner , et al. October 5, 1 | 1999-10-05 |
Reduced bird's beak field oxidation process using nitrogen implanted into active region
Grant 5,962,914 - Gardner , et al. October 5, 1 | 1999-10-05 |
Asymmetrical MOSFET with gate pattern after source/drain formation
Grant 5,963,809 - Duane , et al. October 5, 1 | 1999-10-05 |
Air gap spacer formation for high performance MOSFETs
Grant 5,959,337 - Gardner , et al. September 28, 1 | 1999-09-28 |
Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor
Grant 5,959,333 - Gardner , et al. September 28, 1 | 1999-09-28 |
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