Garde; Douglas

Patent Applications and Registrations

Patent applications and USPTO patent grants for Garde; Douglas.The latest application filed is for "processor architectures for enhanced computational capability and low latency".

Company Profile

0.18.2

Garde; Douglas - Dover MA
Garde; Douglas - Woburn MA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Processor architectures for enhanced computational capability and low latency Grant 8,108,653 - Lerner , et al. January 31, 2	2012-01-31
Processor architectures for enhanced computational capability Grant 8,078,834 - Garde December 13, 2	2011-12-13
Processor Architectures For Enhanced Computational Capability And Low Latency App 20100174883 - Lerner; Boris ; et al.	2010-07-08
Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer Grant RE40,904 - Garde September 1, 2	2009-09-01
Processor architectures for enhanced computational capability App 20090177867 - Garde; Douglas	2009-07-09
Digital signal processor with bit FIFO Grant 6,332,188 - Garde , et al. December 18, 2	2001-12-18
Digital signal processor having data alignment buffer for performing unaligned data accesses Grant 6,061,779 - Garde May 9, 2	2000-05-09
Bidirectional communication port for digital signal processor Grant 6,002,882 - Garde December 14, 1	1999-12-14
Digital signal processor architecture Grant 5,954,811 - Garde September 21, 1	1999-09-21
Digital signal processor architecture Grant 5,896,543 - Garde April 20, 1	1999-04-20
Digital signal processor configured for multiprocessing Grant 5,685,005 - Garde , et al. November 4, 1	1997-11-04
DMA controller responsive to transition of a request signal between first state and second state and maintaining of second state for controlling data transfer Grant 5,634,076 - Garde , et al. May 27, 1	1997-05-27
Apparatus for generating target addresses within a circular buffer including a register for storing position and size of the circular buffer Grant 5,623,621 - Garde April 22, 1	1997-04-22
Digital signal processor having link ports for point-to-point communication Grant 5,619,720 - Garde , et al. April 8, 1	1997-04-08
Bus architecture for digital signal processor allowing time multiplexed access to memory banks Grant 5,611,075 - Garde March 11, 1	1997-03-11
Multi-phase multi-access pipeline memory system Grant 5,471,607 - Garde November 28, 1	1995-11-28
Method and apparatus for accessing variable length words in a memory array Grant 5,396,608 - Garde March 7, 1	1995-03-07
Multi-port register file with flow-through of data Grant 4,811,296 - Garde March 7, 1	1989-03-07
Microprogrammable devices using transparent latch Grant 4,791,551 - Garde December 13, 1	1988-12-13
Addressable Memory Fft Processor With Exponential Term Generation Grant 3,767,905 - Garde October 23, 1	1973-10-23

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