Gao; Pei-Yuan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gao; Pei-Yuan.The latest application filed is for "low-h plasma treatment with n2 anneal for electronic memory devices".

Company Profile

0.12.7

Gao; Pei-Yuan - San Jose CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Low-H plasma treatment with N.sub.2 anneal for electronic memory devices Grant 8,202,810 - Nickel , et al. June 19, 2	2012-06-19
Low-h Plasma Treatment With N2 Anneal For Electronic Memory Devices App 20090176369 - Nickel; Alexander H. ; et al.	2009-07-09
Interlayer dielectric for charge loss improvement Grant 7,300,886 - Ngo , et al. November 27, 2	2007-11-27
Semiconductor memory with data retention liner Grant 7,297,592 - Ngo , et al. November 20, 2	2007-11-20
Method for forming a hardmask employing multiple independently formed layers of a capping material to reduce pinholes Grant 7,183,198 - Gao , et al. February 27, 2	2007-02-27
Semiconductor device and method of fabricating the same App 20060214218 - Shishido; Kiyokazu ; et al.	2006-09-28
PECVD silicon-rich oxide layer for reduced UV charging Grant 7,060,554 - Ngo , et al. June 13, 2	2006-06-13
Multi-chamber deposition of silicon oxynitride film for patterning Grant 7,033,960 - You , et al. April 25, 2	2006-04-25
Undoped oxide liner/BPSG for improved data retention Grant 7,023,046 - Ngo , et al. April 4, 2	2006-04-04
Hardmask employing multiple layers of silicon oxynitride App 20050048771 - Gao, Pei-Yuan ; et al.	2005-03-03
Undoped oxide liner/BPSG for improved data retention App 20050006693 - Ngo, Minh Van ; et al.	2005-01-13
PECVD silicon-rich oxide layer for reduced UV charging App 20050006712 - Ngo, Minh Van ; et al.	2005-01-13
Method for forming a hardmask employing multiple independently formed layers of a pecvd material to reduce pinholes Grant 6,803,313 - Gao , et al. October 12, 2	2004-10-12
Liner for semiconductor memories and manufacturing method therefor Grant 6,803,265 - Ngo , et al. October 12, 2	2004-10-12
Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication Grant 6,764,949 - Bonser , et al. July 20, 2	2004-07-20
Hardmask employing multiple layers of silicon oxynitride App 20040061227 - Gao, Pei-Yuan ; et al.	2004-04-01
Method for reducing pattern deformation and photoresist poisoning in semiconductor device fabrication App 20040023475 - Bonser, Douglas J. ; et al.	2004-02-05
CVD silicon carbide layer as a BARC and hard mask for gate patterning Grant 6,653,735 - Yang , et al. November 25, 2	2003-11-25
Void-free interlayer dielectric (ILD0) for 0.18-micron flash memory semiconductor device Grant 6,627,973 - Ngo , et al. September 30, 2	2003-09-30

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