loadpatents
name:-0.045172929763794
name:-0.37352895736694
name:-0.021497011184692
Gambee; Christopher J. Patent Filings

Gambee; Christopher J.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gambee; Christopher J..The latest application filed is for "die features for self-alignment during die bonding".

Company Profile
17.26.24
  • Gambee; Christopher J. - Caldwell ID
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Die features for self-alignment during die bonding
Grant 11,302,653 - Street , et al. April 12, 2
2022-04-12
Devices with three-dimensional structures and support elements to increase adhesion to substrates
Grant 11,276,658 - Gambee , et al. March 15, 2
2022-03-15
Edge cut debond using a temporary filler material with no adhesive properties and edge cut debond using an engineered carrier to enable topography
Grant 11,094,684 - Tiwari , et al. August 17, 2
2021-08-17
Reduction of roughness on a sidewall of an opening
Grant 10,923,478 - Gambee , et al. February 16, 2
2021-02-16
Semiconductor devices having discretely located passivation material, and associated systems and methods
Grant 10,896,886 - Das , et al. January 19, 2
2021-01-19
Die Features for Self-Alignment During Die Bonding
App 20200373252 - Street; Bret K. ;   et al.
2020-11-26
Devices Three-dimensional Structures To Substrates
App 20200365542 - Gambee; Christopher J. ;   et al.
2020-11-19
Methods of fabricating conductive traces and resulting structures
Grant 10,811,313 - Gambee October 20, 2
2020-10-20
Methods for enhancing adhesion of three-dimensional structures to substrates
Grant 10,790,251 - Gambee , et al. September 29, 2
2020-09-29
Die features for self-alignment during die bonding
Grant 10,748,857 - Street , et al. A
2020-08-18
Reduction Of Roughness On A Sidewall Of An Opening
App 20200243535 - Gambee; Christopher J. ;   et al.
2020-07-30
Die Features for Self-Alignment During Die Bonding
App 20200083178 - Street; Bret K. ;   et al.
2020-03-12
Methods For Enhancing Adhesion Of Three-dimenional Structures To Substrates, And Related Assemblies And Systems
App 20190393176 - Gambee; Christopher J. ;   et al.
2019-12-26
Edge Cut Debond Using a Temporary Filler Material With No Adhesive Properties and Edge Cut Debond Using an Engineered Carrier to
App 20190341378 - Tiwari; Chandra S. ;   et al.
2019-11-07
Edge cut debond using a temporary filler material with no adhesive properties and edge cut debond using an engineered carrier to enable topography
Grant 10,403,618 - Tiwari , et al. Sep
2019-09-03
Methods Of Fabricating Conductive Traces And Resulting Structures
App 20190259660 - Gambee; Christopher J.
2019-08-22
Methods of fabricating conductive traces and resulting structures
Grant 10,332,792 - Gambee
2019-06-25
Semiconductor Devices Having Discretely Located Passivation Material, And Associated Systems And Methods
App 20190189576 - Das; Mayukhee ;   et al.
2019-06-20
Methods Of Fabricating Conductive Traces And Resulting Structures
App 20190189507 - Gambee; Christopher J.
2019-06-20
Semiconductor devices having discretely located passivation material, and associated systems and methods
Grant 10,262,961 - Das , et al.
2019-04-16
Edge Cut Debond Using a Temporary Filler Material With No Adhesive Properties and Edge Cut Debond Using an Engineered Carrier to Enable Topography
App 20190088637 - Tiwari; Chandra S. ;   et al.
2019-03-21
Semiconductor Devices Having Discretely Located Passivation Material, And Associated Systems And Methods
App 20190051623 - Das; Mayukhee ;   et al.
2019-02-14
Semiconductor devices having discretely located passivation material, and associated systems and methods
Grant 10,002,840 - Das , et al. June 19, 2
2018-06-19
Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
Grant 9,966,347 - Wirz , et al. May 8, 2
2018-05-08
Under-bump Metal Structures For Interconnecting Semiconductor Dies Or Packages And Associated Systems And Methods
App 20170287857 - Wirz; Brandon P. ;   et al.
2017-10-05
Semiconductor devices and methods for backside photo alignment
Grant 9,741,612 - Wirz , et al. August 22, 2
2017-08-22
Under-bump metal structures for interconnecting semiconductor dies or packages and associated systems and methods
Grant 9,704,781 - Wirz , et al. July 11, 2
2017-07-11
Semiconductor Devices And Methods For Backside Photo Alignment
App 20160172242 - Wirz; Brandon P. ;   et al.
2016-06-16
Semiconductor structures comprising at least one through-substrate via filled with conductive materials
Grant 9,318,438 - Bossler , et al. April 19, 2
2016-04-19
Semiconductor devices and methods for backside photo alignment
Grant 9,299,663 - Wirz , et al. March 29, 2
2016-03-29
Semiconductor Devices And Methods For Backside Photo Alignment
App 20150333014 - Wirz; Brandon P. ;   et al.
2015-11-19
Pillar on pad interconnect structures, semiconductor devices including same and related methods
Grant 9,129,869 - Fay , et al. September 8, 2
2015-09-08
Semiconductor structures comprising at least one through-substrate via filled with conductive materials
App 20150214160 - Bossler; Mark A. ;   et al.
2015-07-30
Under-bump Metal Structures For Interconnecting Semiconductor Dies Or Packages And Associated Systems And Methods
App 20150137353 - Wirz; Brandon P. ;   et al.
2015-05-21
Methods of selectively removing a substrate material
Grant 9,034,769 - Bossler , et al. May 19, 2
2015-05-19
Pillar On Pad Interconnect Structures, Semiconductor Devices Including Same And Related Methods
App 20140167259 - Fay; Owen R. ;   et al.
2014-06-19
Methods Of Selectively Removing A Substrate Material And Related Semiconductor Structures
App 20140159239 - Bossler; Mark A. ;   et al.
2014-06-12
Pillar on pad interconnect structures, semiconductor dice and die assemblies including such interconnect structures, and related methods
Grant 8,659,153 - Fay , et al. February 25, 2
2014-02-25
Pillar On Pad Interconnect Structures, Semiconductor Dice And Die Assemblies Including Such Interconnect Structures, And Related Methods
App 20140015124 - Fay; Owen R. ;   et al.
2014-01-16
Methods of forming a metal pattern
Grant 8,470,710 - Gambee , et al. June 25, 2
2013-06-25
Methods Of Forming A Metal Pattern
App 20130005145 - Gambee; Christopher J. ;   et al.
2013-01-03
Methods of forming a metal pattern and semiconductor device structure
Grant 8,329,580 - Gambee , et al. December 11, 2
2012-12-11
Methods Of Forming A Metal Pattern And Semiconductor Device Structure
App 20110210451 - Gambee; Christopher J. ;   et al.
2011-09-01
Method to create a metal pattern using a damascene-like process
Grant 8,008,196 - Gambee , et al. August 30, 2
2011-08-30
Method To Create A Metal Pattern Using A Damascene-like Process
App 20080248645 - Gambee; Christopher J. ;   et al.
2008-10-09
Intermediate semiconductor device structures
Grant 7,402,908 - Gambee , et al. July 22, 2
2008-07-22
Method to create a metal pattern using a damascene-like process and associated structures
App 20060252225 - Gambee; Christopher J. ;   et al.
2006-11-09

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