Gaitonde; Dinesh D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gaitonde; Dinesh D..The latest application filed is for "configurable network-on-chip for a programmable device".

Company Profile

4.16.3

Gaitonde; Dinesh D. - Fremont CA
Gaitonde; Dinesh D. - San Mateo CA
Gaitonde; Dinesh D. - Chandler AZ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Configurable network-on-chip for a programmable device Grant 10,838,908 - Swarbrick , et al. November 17, 2	2020-11-17
Resolving timing violations in multi-die circuit designs Grant 10,747,929 - Fraisse , et al. A	2020-08-18
Routing circuit designs for implementation using a programmable network on chip Grant 10,628,547 - Swarbrick , et al.	2020-04-21
Performing placement and routing concurrently Grant 10,614,191 - Fraisse , et al.	2020-04-07
Placement, routing, and deadlock removal for network-on-chip using integer linear programming Grant 10,565,346 - Suthar , et al. Feb	2020-02-18
Configurable Network-on-chip For A Programmable Device App 20200026684 - Swarbrick; Ian A. ; et al.	2020-01-23
Placing and routing an interface portion and a main portion of a circuit design Grant 10,503,861 - Gaitonde , et al. Dec	2019-12-10
Re-budgeting connections of a circuit design Grant 8,972,920 - Gasparyan , et al. March 3, 2	2015-03-03
Clock network architecture Grant 8,937,491 - Gaide , et al. January 20, 2	2015-01-20
Clock Network Architecture App 20140132305 - Gaide; Brian C. ; et al.	2014-05-15
Creating a standard cell circuit design from a programmable logic device circuit design Grant 8,667,437 - Raje , et al. March 4, 2	2014-03-04
Global placement legalization for complex packing rules Grant 8,219,957 - Gaitonde , et al. July 10, 2	2012-07-10
Clock speed for a digital circuit Grant 8,024,696 - Srinivasan , et al. September 20, 2	2011-09-20
Timing analysis of a mapped logic design using physical delays Grant 7,886,256 - Jha , et al. February 8, 2	2011-02-08
Automatic pin placement for integrated circuits to aid circuit board design Grant 7,594,212 - Gaitonde , et al. September 22, 2	2009-09-22
Creating A Standard Cell Circuit Design From A Programmable Logic Device Circuit Design App 20090235222 - Raje; Salil Ravindra ; et al.	2009-09-17
Method and apparatus for generating sign-off prototypes for the design and fabrication of integrated circuits Grant 6,775,808 - Raje , et al. August 10, 2	2004-08-10
Architectural power estimation method and apparatus Grant 5,940,779 - Gaitonde , et al. August 17, 1	1999-08-17

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