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Patent applications and USPTO patent grants for Gaibotti; Maurizio.The latest application filed is for "voltage down-converter with reduced ripple".
Patent | Date |
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Architecture for implementing an integrated capacitance Grant 7,414,459 - Pisasale , et al. August 19, 2 | 2008-08-19 |
Voltage down-converter with reduced ripple Grant 7,385,377 - Pisasale , et al. June 10, 2 | 2008-06-10 |
Voltage down-converter with reduced ripple App 20060164888 - Pisasale; Michelangelo ;   et al. | 2006-07-27 |
Voltage down converter App 20060103453 - Pisasale; Michelangelo ;   et al. | 2006-05-18 |
Integrated charge pump voltage booster Grant 6,943,615 - Pappalardo , et al. September 13, 2 | 2005-09-13 |
Variable stage charge pump Grant 6,927,441 - Pappalardo , et al. August 9, 2 | 2005-08-09 |
Generator circuit for voltage ramps and corresponding voltage generation method Grant 6,650,153 - Zerilli , et al. November 18, 2 | 2003-11-18 |
Integrated charge pump voltage booster App 20030174010 - Pappalardo, Domenico ;   et al. | 2003-09-18 |
Variable stage charge pump App 20020163376 - Pappalardo, Domenico ;   et al. | 2002-11-07 |
Generator circuit for voltage ramps and corresponding voltage generation method App 20020153928 - Zerilli, Tommaso ;   et al. | 2002-10-24 |
Sense amplifier for low voltage memories Grant 6,466,059 - Gaibotti , et al. October 15, 2 | 2002-10-15 |
Memory read amplifier circuit with high current level discrimination capacity Grant 6,320,808 - Conte , et al. November 20, 2 | 2001-11-20 |
CMOS technology voltage booster App 20010022526 - Coco, Luca Lo ;   et al. | 2001-09-20 |
Temperature-stable current generation Grant 6,133,718 - Calafato , et al. October 17, 2 | 2000-10-17 |
Integrated shielded electric connection Grant 6,133,621 - Gaibotti , et al. October 17, 2 | 2000-10-17 |
Low consumption boosted voltage driving circuit Grant 6,130,844 - Zerilli , et al. October 10, 2 | 2000-10-10 |
Voltage boosting circuit for generating boosted voltage phases Grant 6,064,594 - Calafato , et al. May 16, 2 | 2000-05-16 |
Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit Grant RE36,292 - September 7, 1 | 1999-09-07 |
Low-consumption and high-density D flip-flop circuit implementation particularly for standard cell libraries Grant 5,821,791 - Gaibotti , et al. October 13, 1 | 1998-10-13 |
Operational analysis device of the scan path type having a single scanning clock and a single output phase for an integrated circuit Grant 5,225,724 - Scarra' , et al. July 6, 1 | 1993-07-06 |
Voltage supply switching device for nonvolatile memories in MOS technology Grant 5,003,511 - Secol , et al. March 26, 1 | 1991-03-26 |
Power-on reset circuit for MOS logic devices Grant 4,797,584 - Aguti , et al. January 10, 1 | 1989-01-10 |
Integrated structure microcomputer provided with non-volatile RAM memory Grant 4,638,465 - Rosini , et al. January 20, 1 | 1987-01-20 |
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