Gabriel; Calvin Todd

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gabriel; Calvin Todd.The latest application filed is for "optimized gate implants for reducing dopant effects during gate etching".

Company Profile

0.16.2

Gabriel; Calvin Todd - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Optimized gate implants for reducing dopant effects during gate etching Grant 6,822,291 - Gabriel , et al. November 23, 2	2004-11-23
Etch process that resists notching at electrode bottom Grant 6,794,294 - Zheng , et al. September 21, 2	2004-09-21
Semiconductor blocking layer for preventing UV radiation damage to MOS gate oxides Grant 6,627,536 - Gabriel September 30, 2	2003-09-30
Optimized gate implants for reducing dopant effects during gate etching App 20030146472 - Gabriel, Calvin Todd ; et al.	2003-08-07
Methods for forming co-axial interconnect lines in a CMOS process for high speed applications Grant 6,569,757 - Weling , et al. May 27, 2	2003-05-27
Methods for implementing co-axial interconnect lines in a CMOS process for high speed RF and microwave applications Grant 6,545,338 - Bothra , et al. April 8, 2	2003-04-08
Semiconductor blocking layer for preventing UV radiation damage to MOS gate oxides Grant 6,410,210 - Gabriel June 25, 2	2002-06-25
Method for reducing the amount of perfluorocompound gas contained in exhaust emissions from plasma processing Grant 6,361,706 - Gabriel March 26, 2	2002-03-26
Method for a consistent shallow trench etch profile Grant 6,342,428 - Zheng , et al. January 29, 2	2002-01-29
Sacrificial multilayer anti-reflective coating for mos gate formation Grant 6,297,170 - Gabriel , et al. October 2, 2	2001-10-02
Optimized metal etch process to enable the use of aluminum plugs App 20010012690 - Zheng, Tammy ; et al.	2001-08-09
Optimized metal etch process to enable the use of aluminum plugs Grant 6,255,226 - Zheng , et al. July 3, 2	2001-07-03
Method of manufacturing a trench structure in a semiconductor substrate Grant 6,107,158 - Zheng , et al. August 22, 2	2000-08-22
Silicon-enriched shallow trench oxide for reduced recess during LDD spacer etch Grant 6,013,558 - Harvey , et al. January 11, 2	2000-01-11
Sidewall profile Grant 5,939,765 - Zheng , et al. August 17, 1	1999-08-17
Trench isolation method Grant 5,882,982 - Zheng , et al. March 16, 1	1999-03-16
Method for achieving accurate SOG etchback selectivity Grant 5,821,163 - Harvey , et al. October 13, 1	1998-10-13
Method for forming a reduced width gate electrode Grant 5,776,821 - Haskell , et al. July 7, 1	1998-07-07

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