Gabriel; Calvin

Patent Applications and Registrations

Patent applications and USPTO patent grants for Gabriel; Calvin.The latest application filed is for "charge trapping split gate embedded flash memory and associated methods".

Company Profile

0.10.7

Gabriel; Calvin - Cupertino CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Charge trapping split gate embedded flash memory and associated methods Grant 9,922,833 - Ramsbey , et al. March 20, 2	2018-03-20
Charge Trapping Split Gate Embedded Flash Memory And Associated Methods App 20160111292 - RAMSBEY; Mark ; et al.	2016-04-21
Charge Trapping Split Gate Embedded Flash Memory and Associated Methods App 20140167141 - RAMSBEY; Mark ; et al.	2014-06-19
Self-aligned patterning method by using non-conformal film and etch for flash memory and other semiconductor applications Grant 8,035,153 - Fang , et al. October 11, 2	2011-10-11
Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics Grant 7,906,807 - Cheng , et al. March 15, 2	2011-03-15
Use Of A Polymer Spacer And Si Trench In A Bitline Junction Of A Flash Memory Cell To Improve Tpd Characteristics App 20100264480 - Cheng; Ning ; et al.	2010-10-21
Self-aligned Patterning Method By Using Non-conformal Film And Etch For Flash Memory And Other Semiconductor Applications App 20100230743 - Fang; Shenqing ; et al.	2010-09-16
Use of a polymer spacer and Si trench in a bitline junction of a flash memory cell to improve TPD characteristics Grant 7,776,688 - Cheng , et al. August 17, 2	2010-08-17
Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications Grant 7,732,276 - Fang , et al. June 8, 2	2010-06-08
Use Of A Polymer Spacer And Si Trench In A Bitline Junction Of A Flash Memory Cell To Improve Tpd Characteristics App 20090042378 - Cheng; Ning ; et al.	2009-02-12
Thin film germanium diode with low reverse breakdown Grant 7,468,296 - Adem , et al. December 23, 2	2008-12-23
Self-aligned patterning method by using non-conformal film and etch back for flash memory and other semiconductor applications App 20080265301 - Fang; Shenqing ; et al.	2008-10-30
Selective etch shallow trench isolation barrier integrated circuit chip and fabrication method App 20050073021 - Gabriel, Calvin ; et al.	2005-04-07
Vapor treatment for repairing damage of low-k dielectric Grant 6,713,382 - Pangrle , et al. March 30, 2	2004-03-30
Chemical wet etch removal of underlayer material after performing chemical mechanical polishing on a primary layer Grant 6,211,087 - Gabriel , et al. April 3, 2	2001-04-03
Integrated etch process for polysilicon/metal gate Grant 6,060,376 - Gabriel , et al. May 9, 2	2000-05-09
Complementary material conditioning system for a chemical mechanical polishing machine Grant 6,022,265 - Drill , et al. February 8, 2	2000-02-08

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.