loadpatents
name:-0.0032179355621338
name:-0.019721984863281
name:-0.00037908554077148
Furtek; Frederick C. Patent Filings

Furtek; Frederick C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Furtek; Frederick C..The latest application filed is for "automatically deriving logical, arithmetic and timing dependencies".

Company Profile
0.18.1
  • Furtek; Frederick C. - Menlo Park CA
  • Furtek; Frederick C. - Arlington MA
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Automatically deriving logical, arithmetic and timing dependencies
Grant 7,516,109 - Furtek April 7, 2
2009-04-07
Automatically deriving logical, arithmetic and timing dependencies
App 20060167664 - Furtek; Frederick C.
2006-07-27
System and method for verifying logical, arithmetic and timing dependencies of system behaviors using constraint calculus analysis
Grant 6,820,068 - Furtek November 16, 2
2004-11-16
FPGA structure having main, column and sector reset lines
Grant 6,292,021 - Furtek , et al. September 18, 2
2001-09-18
FPGA structure having main, column and sector clock lines
Grant 6,167,559 - Furtek , et al. December 26, 2
2000-12-26
FPGA logic cell internal structure including pair of look-up tables
Grant 6,026,227 - Furtek , et al. February 15, 2
2000-02-15
Field programmable gate array having access to orthogonal and diagonal adjacent neighboring cells
Grant 6,014,509 - Furtek , et al. January 11, 2
2000-01-11
Field programmable gate array with distributed RAM and increased cell utilization
Grant 5,894,565 - Furtek , et al. April 13, 1
1999-04-13
Method and apparatus for comparing data sets
Grant 5,504,931 - Furtek April 2, 1
1996-04-02
Method and apparatus for motion estimation
Grant 5,430,886 - Furtek July 4, 1
1995-07-04
Versatile programmable logic cell for use in configurable logic arrays
Grant 5,245,227 - Furtek , et al. September 14, 1
1993-09-14
Programmable logic cell and array with bus repeaters
Grant 5,218,240 - Camarota , et al. June 8, 1
1993-06-08
Programmable logic cell and array
Grant 5,155,389 - Furtek * October 13, 1
1992-10-13
Programmable logic cell and array
Grant 5,144,166 - Camarota , et al. September 1, 1
1992-09-01
Programmable logic cell and array
Grant 5,089,973 - Furtek February 18, 1
1992-02-18
Programmable logic cell and array
Grant 5,019,736 - Furtek May 28, 1
1991-05-28
Programmable logic cell and array
Grant 4,918,440 - Furtek April 17, 1
1990-04-17
System for programming graphically a programmable, asynchronous logic cell and array
Grant 4,845,633 - Furtek July 4, 1
1989-07-04
Programmable, asynchronous logic cell and array
Grant 4,700,187 - Furtek October 13, 1
1987-10-13

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2025 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed