Funabashi; Tsuneo
Patent Applications and Registrations
Patent applications and USPTO patent grants for Funabashi; Tsuneo.The latest application filed is for "hierarchal system for reducing memory access time to plural equal sized memories by simultaneously addressing and accessing memory".
- Funabashi; Tsuneo - Tokyo JP
- Funabashi; Tsuneo - Hachioji JP
- Funabashi; Tsuneo - Bunkyo JP
| Patent | Date |
|---|---|
| Hierarchal system for reducing memory access time to plural equal sized memories by simultaneously addressing and accessing memory Grant 5,047,920 - Funabashi September 10, 1 | 1991-09-10 |
| Data processing system with coprocessor Grant 4,894,768 - Iwasaki , et al. January 16, 1 | 1990-01-16 |
| Microcomputer system with buffer in peripheral storage control Grant 4,716,522 - Funabashi , et al. December 29, 1 | 1987-12-29 |
| Decoding method and apparatus for cyclic codes Grant 4,677,623 - Iwasaki , et al. June 30, 1 | 1987-06-30 |
| Data processing system with an enhanced communication control system Grant 4,674,037 - Funabashi , et al. June 16, 1 | 1987-06-16 |
| Pulse frequency multiplier circuit Grant 4,353,030 - Nakamura , et al. October 5, 1 | 1982-10-05 |
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