Fuller; Nicholas C.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fuller; Nicholas C..The latest application filed is for "interconnect structures with fully aligned vias".

Company Profile

4.27.34

Fuller; Nicholas C. - North Hills NY
Fuller; Nicholas C. - Armonk NY
Fuller; Nicholas C. - New York NY
Fuller; Nicholas C - North Hills NY
Fuller; Nicholas C. - Ossining NY
Fuller; Nicholas C. - Elmsford NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Interconnect structures with fully aligned vias Grant 10,607,933 - Edelstein , et al.	2020-03-31
Enhanced via fill material and processing for dual damscene integration Grant 10,340,182 - Doyle , et al.	2019-07-02
Interconnect Structures With Fully Aligned Vias App 20190157201 - Edelstein; Daniel C. ; et al.	2019-05-23
Interconnect structures with fully aligned vias Grant 10,204,856 - Edelstein , et al. Feb	2019-02-12
Enhanced Via Fill Material And Processing For Dual Damascene Integration App 20180138084 - Doyle; James P. ; et al.	2018-05-17
Interconnect Structures With Fully Aligned Vias App 20180102317 - Edelstein; Daniel C. ; et al.	2018-04-12
Interconnect structures with fully aligned vias Grant 9,911,690 - Edelstein , et al. March 6, 2	2018-03-06
Dynamic resource allocation in MapReduce Grant 9,886,310 - Fuller , et al. February 6, 2	2018-02-06
Enabling dynamic job configuration in mapreduce Grant 9,766,940 - Fuller , et al. September 19, 2	2017-09-19
Enhanced Via Fill Material And Processing For Dual Damscene Integration App 20170154812 - DOYLE; James P. ; et al.	2017-06-01
Dynamic tuning of memory in MapReduce systems Grant 9,582,189 - Fuller , et al. February 28, 2	2017-02-28
Interconnect Structures With Fully Aligned Vias App 20160163640 - Edelstein; Daniel C. ; et al.	2016-06-09
Interconnect structures with fully aligned vias Grant 9,324,650 - Edelstein , et al. April 26, 2	2016-04-26
Interconnect Structures With Fully Aligned Vias App 20160049364 - Edelstein; Daniel C. ; et al.	2016-02-18
Dynamic Tuning of Memory in MapReduce Systems App 20150309731 - Fuller; Nicholas C. ; et al.	2015-10-29
Cost Optimization for Bundled Licenses App 20150248690 - Fan; Li Ya ; et al.	2015-09-03
Dynamic Resource Allocation in Mapreduce App 20150227393 - Fuller; Nicholas C. ; et al.	2015-08-13
Enabling Dynamic Job Configuration in Mapreduce App 20150227392 - Fuller; Nicholas C. ; et al.	2015-08-13
Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors Grant 9,006,108 - Fuller , et al. April 14, 2	2015-04-14
Methodology For Fabricating Isotropically Recessed Source Regions Of Cmos Transistors App 20140231809 - Fuller; Nicholas C. ; et al.	2014-08-21
Self-aligned borderless contacts for high density electronic and memory device integration Grant 8,754,530 - Babich , et al. June 17, 2	2014-06-17
Methodology for fabricating isotropically recessed source and drain regions of CMOS transistors Grant 8,716,798 - Fuller , et al. May 6, 2	2014-05-06
Optimized License Procurement App 20140122160 - Fuller; Nicholas C. ; et al.	2014-05-01
Optimized License Procurement App 20140122348 - Fuller; Nicholas C. ; et al.	2014-05-01
Methodology For Fabricating Isotropically Recessed Drain Regions Of Cmos Transistors App 20130146965 - Fuller; Nicholas C. ; et al.	2013-06-13
Methodology for fabricating isotropically recessed drain regions of CMOS transistors Grant 8,431,995 - Fuller , et al. April 30, 2	2013-04-30
Methodology For Fabricating Isotropically Recessed Source And Drain Regions Of Cmos Transistors App 20130012026 - Fuller; Nicholas C. ; et al.	2013-01-10
Mixed lithography with dual resist and a single pattern transfer Grant 8,334,090 - Fuller , et al. December 18, 2	2012-12-18
Methodology For Fabricating Isotropically Recessed Source Regions Of Cmos Transistors App 20120305928 - Fuller; Nicholas C. ; et al.	2012-12-06
Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application Grant 8,159,042 - Yang , et al. April 17, 2	2012-04-17
Trilayer resist scheme for gate etching applications Grant 8,084,825 - Fuller , et al. December 27, 2	2011-12-27
Methodology For Fabricating Isotropically Recessed Drain Regions Of Cmos Transistors App 20110278672 - Fuller; Nicholas C. ; et al.	2011-11-17
Methodology For Fabricating Isotropically Source Regions Of Cmos Transistors App 20110278580 - Fuller; Nicholas C. ; et al.	2011-11-17
Methodology For Fabricating Isotropically Recessed Source And Drain Regions Of Cmos Transistors App 20110278673 - Fuller; Nicholas C. ; et al.	2011-11-17
System and method for plasma induced modification and improvement of critical dimension uniformity Grant 8,049,335 - Dalton , et al. November 1, 2	2011-11-01
Mixed Lithography With Dual Resist And A Single Pattern Transfer App 20110123779 - Fuller; Nicholas C. ; et al.	2011-05-26
Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application Grant 7,927,995 - Yang , et al. April 19, 2	2011-04-19
Mixed lithography with dual resist and a single pattern transfer Grant 7,914,970 - Fuller , et al. March 29, 2	2011-03-29
Self-aligned Borderless Contacts For High Density Electronic And Memory Device Integration App 20100038723 - Babich; Katherina E. ; et al.	2010-02-18
Adopting Feature Of Buried Electrically Conductive Layer In Dielectrics For Electrical Anti-fuse Application App 20090305493 - Yang; Chih-Chao ; et al.	2009-12-10
Interconnect Structures With Partially Self Aligned Vias And Methods To Produce Same App 20090200683 - Colburn; Matthew Earl ; et al.	2009-08-13
Plasma Curing Of Patterning Materials For Aggressively Scaled Features App 20090174036 - Fuller; Nicholas C. ; et al.	2009-07-09
Trilayer Resist Scheme For Gate Etching Applications App 20090101985 - Fuller; Nicholas C. ; et al.	2009-04-23
Mixed Lithography With Dual Resist And A Single Pattern Transfer App 20090092799 - Fuller; Nicholas C. ; et al.	2009-04-09
Dual Damascene Process Flow Enabling Minimal Ulk Film Modification And Enhanced Stack Integrity App 20090014880 - Dalton; Timothy J. ; et al.	2009-01-15
Adopting Feature Of Buried Electrically Conductive Layer In Dielectrics For Electrical Anti-fuse Application App 20080283964 - Yang; Chih-Chao ; et al.	2008-11-20
Trilayer resist scheme for gate etching applications Grant 7,435,671 - Fuller , et al. October 14, 2	2008-10-14
Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity Grant 7,435,676 - Dalton , et al. October 14, 2	2008-10-14
Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application Grant 7,402,463 - Yang , et al. July 22, 2	2008-07-22
Trilayer resist scheme for gate etching applications App 20080045011 - Fuller; Nicholas C. ; et al.	2008-02-21
De-fluorination after via etch to preserve passivation Grant 7,282,441 - Fuller , et al. October 16, 2	2007-10-16
Dual damascene process flow enabling minimal ULK film modification and enhanced stack integrity App 20070161226 - Dalton; Timothy J. ; et al.	2007-07-12
System And Method For Plasma Induced Modification And Improvement Of Critical Dimension Uniformity App 20070143721 - Dalton; Timothy J. ; et al.	2007-06-21
System and method for plasma induced modification and improvement of critical dimension uniformity Grant 7,196,014 - Dalton , et al. March 27, 2	2007-03-27
Adopting feature of buried electrically conductive layer in dielectrics for electrical anti-fuse application App 20070040276 - Yang; Chih-Chao ; et al.	2007-02-22
System and method for plasma induced modification and improvement of critical dimension uniformity App 20060099816 - Dalton; Timothy J. ; et al.	2006-05-11

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