Fuller; Douglas A

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fuller; Douglas A.The latest application filed is for "systems and methods for implementing a multi-host record lock mechanism".

Company Profile

4.14.4

Fuller; Douglas A - Roseville MN US
Fuller; Douglas A. - Roseville MN
Fuller; Douglas A. - Eagan MN

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Systems and methods for implementing a multi-host record lock deadlock feedback mechanism Grant 10,635,653 - Trautman , et al.	2020-04-28
Systems and methods for implementing a multi-host record lock mechanism Grant 10,423,603 - Otto , et al. Sept	2019-09-24
Systems And Methods For Implementing A Multi-host Record Lock Mechanism App 20170364545 - Otto; MICHAEL C. ; et al.	2017-12-21
Systems And Methods For Implementing A Multi-host Record Lock Deadlock Feedback Mechanism App 20170308564 - Trautman; Matthew E. ; et al.	2017-10-26
System and method for detecting and recovering from errors in a control store of an electronic data processing system Grant 7,562,263 - Engelbrecht , et al. July 14, 2	2009-07-14
System and method to support dynamic partitioning of units to a shared resource Grant 7,478,025 - Fuller , et al. January 13, 2	2009-01-13
Cache with integrated capability to write out entire cache Grant 7,356,647 - Andrighetti , et al. April 8, 2	2008-04-08
First level cache parity error inject Grant 6,751,756 - Hartnett , et al. June 15, 2	2004-06-15
Event counter Grant 6,542,985 - Johnson , et al. April 1, 2	2003-04-01
Method of using a four-state simulator for testing integrated circuit designs having variable timing constraints Grant 5,819,072 - Bushard , et al. October 6, 1	1998-10-06
Method and apparatus for performing microcode paging during instruction execution in an instruction processor Grant 5,796,972 - Johnson , et al. August 18, 1	1998-08-18
Method and apparatus for resolving conflicts between cell substitution recommendations provided by a drive strength adjust tool Grant 5,726,903 - Kerzman , et al. March 10, 1	1998-03-10
Method and apparatus for performing drive strength adjust optimization in a circuit design Grant 5,724,250 - Kerzman , et al. March 3, 1	1998-03-03
Method and apparatus for performing timing analysis on a circuit design Grant 5,719,783 - Kerzman , et al. February 17, 1	1998-02-17

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