| Patent | Date |
|---|
Ultrathin high-K gate dielectric with favorable interface properties for improved semiconductor device performance
Grant 6,911,707 - Gardner , et al. June 28, 2 | 2005-06-28 |
Tri-level segmented control transistor and fabrication method
Grant 6,661,057 - Dawson , et al. December 9, 2 | 2003-12-09 |
Photolithographic system including light filter that compensates for lens error
Grant 6,552,776 - Wristers , et al. April 22, 2 | 2003-04-22 |
Dopant diffusion-retarding barrier region formed within polysilicon gate layer
Grant 6,380,055 - Gardner , et al. April 30, 2 | 2002-04-30 |
Dielectric having an air gap formed between closely spaced interconnect lines
Grant 6,376,330 - Fulford, Jr. , et al. April 23, 2 | 2002-04-23 |
Semiconductor topography having improved active device isolation and reduced dopant migration
Grant 6,362,510 - Gardner , et al. March 26, 2 | 2002-03-26 |
Dopant Diffusion-retarding Barrier Region Formed Within Polysilicon Gate Layer
App 20020004294 - GARDNER, MARK I. ; et al. | 2002-01-10 |
Method Of Making An Igfet Using Solid Phase Diffusion To Dope The Gate, Source And Drain
App 20010039094 - WRISTERS, DERICK J. ; et al. | 2001-11-08 |
Dielectrically-isolated transistor with low-resistance metal source and drain formed using sacrificial source and drain structures
Grant 6,303,962 - Gardner , et al. October 16, 2 | 2001-10-16 |
Transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection
Grant 6,297,535 - Gardner , et al. October 2, 2 | 2001-10-02 |
Multiple split gate semiconductor device and fabrication method
Grant 6,259,142 - Dawson , et al. July 10, 2 | 2001-07-10 |
Integrated circuit gate conductor which uses layered spacers to produce a graded junction
Grant 6,258,680 - Fulford, Jr. , et al. July 10, 2 | 2001-07-10 |
Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit
Grant 6,255,698 - Gardner , et al. July 3, 2 | 2001-07-03 |
Nitrogen liner beneath transistor source/drain regions to retard dopant diffusion
Grant 6,225,151 - Gardner , et al. May 1, 2 | 2001-05-01 |
Interlevel dielectric with air gaps to lessen capacitive coupling
Grant 6,208,015 - Bandyopadhyay , et al. March 27, 2 | 2001-03-27 |
Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device
Grant 6,204,153 - Gardner , et al. March 20, 2 | 2001-03-20 |
Use of sacrificial dielectric structure to form semiconductor device with a self-aligned threshold adjust and overlying low-resistance gate
Grant 6,200,865 - Gardner , et al. March 13, 2 | 2001-03-13 |
Trench transistor with insulative spacers
Grant 6,201,278 - Gardner , et al. March 13, 2 | 2001-03-13 |
Method of making an IGFET with elevated source/drain regions in close proximity to gate with sloped sidewalls
Grant 6,197,645 - Michael , et al. March 6, 2 | 2001-03-06 |
Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions
Grant 6,187,620 - Fulford, Jr. , et al. February 13, 2 | 2001-02-13 |
Method of forming an insulated-gate field-effect transistor with metal spacers
Grant 6,188,114 - Gardner , et al. February 13, 2 | 2001-02-13 |
Method and structure for isolating semiconductor devices after transistor formation
Grant 6,184,566 - Gardner , et al. February 6, 2 | 2001-02-06 |
High-reliability damascene interconnect formation for semiconductor fabrication
Grant 6,157,081 - Nariman , et al. December 5, 2 | 2000-12-05 |
Integrated circuit having interconnect lines separated by a dielectric having a capping layer
Grant 6,153,833 - Dawson , et al. November 28, 2 | 2000-11-28 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines
Grant 6,150,721 - Bandyopadhyay , et al. November 21, 2 | 2000-11-21 |
Integrated circuit having an interlevel interconnect coupled to a source/drain region(s) with source/drain region(s) boundary overlap and reduced parasitic capacitance
Grant 6,146,978 - Michael , et al. November 14, 2 | 2000-11-14 |
Ultrathin silicon nitride containing sidewall spacers for improved transistor performance
Grant 6,144,071 - Gardner , et al. November 7, 2 | 2000-11-07 |
Trench isolation structure having a low K dielectric material isolated from a silicon-based substrate
Grant 6,140,691 - Gardner , et al. October 31, 2 | 2000-10-31 |
Integrated circuit having conductors of enhanced cross-sectional area
Grant 6,127,264 - Bandyopadhyay , et al. October 3, 2 | 2000-10-03 |
Selective spacer formation for optimized silicon area reduction
Grant 6,121,099 - Fulford, Jr. , et al. September 19, 2 | 2000-09-19 |
Test structure responsive to electrical signals for determining lithographic misalignment of conductors relative to vias
Grant 6,118,137 - Fulford, Jr. , et al. September 12, 2 | 2000-09-12 |
CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions
Grant 6,107,130 - Fulford, Jr. , et al. August 22, 2 | 2000-08-22 |
Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance
Grant 6,107,129 - Gardner , et al. August 22, 2 | 2000-08-22 |
Multiple spacer formation/removal technique for forming a graded junction
Grant 6,104,063 - Fulford, Jr. , et al. August 15, 2 | 2000-08-15 |
Method of forming trench transistor with insulative spacers
Grant 6,100,146 - Gardner , et al. August 8, 2 | 2000-08-08 |
Forming a self-aligned silicide gate conductor to a greater thickness than junction silicide structures using a dual-salicidation process
Grant 6,100,173 - Gardner , et al. August 8, 2 | 2000-08-08 |
Oxide liner for high reliability with reduced encroachment of the source/drain region
Grant 6,093,611 - Gardner , et al. July 25, 2 | 2000-07-25 |
Dissolvable dielectric method and structure
Grant 6,091,149 - Hause , et al. July 18, 2 | 2000-07-18 |
Trench isolation structure partially bound between a pair of low K dielectric structures
Grant 6,087,705 - Gardner , et al. July 11, 2 | 2000-07-11 |
Compact transistor structure with adjacent trench isolation and source/drain regions implanted vertically into trench walls
Grant 6,087,706 - Dawson , et al. July 11, 2 | 2000-07-11 |
Subtrench conductor formed with large tilt angle implant
Grant 6,066,885 - Fulford, Jr. , et al. May 23, 2 | 2000-05-23 |
Method of making NMOS and PMOS devices with reduced masking steps
Grant 6,060,345 - Hause , et al. May 9, 2 | 2000-05-09 |
Method of stitching segments defined by adjacent image patterns during the manufacture of a semiconductor device
Grant 6,030,752 - Fulford, Jr. , et al. February 29, 2 | 2000-02-29 |
Integrated circuit which uses a recessed local conductor for producing staggered interconnect lines
Grant 6,031,289 - Fulford, Jr. , et al. February 29, 2 | 2000-02-29 |
Trench isolation structure having a low K dielectric encapsulated by oxide
Grant 6,008,109 - Fulford, Jr. , et al. December 28, 1 | 1999-12-28 |
Argon doped epitaxial layers for inhibiting punchthrough within a semiconductor device
Grant 6,005,285 - Gardner , et al. December 21, 1 | 1999-12-21 |
Ultra thin spacers formed laterally adjacent a gate conductor recessed below the upper surface of a substrate
Grant 5,998,288 - Gardner , et al. December 7, 1 | 1999-12-07 |
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect
Grant 5,998,293 - Dawson , et al. December 7, 1 | 1999-12-07 |
Method of controlling dopant concentrations using transient-enhanced diffusion prior to gate formation in a device
Grant 5,976,956 - Gardner , et al. November 2, 1 | 1999-11-02 |
Method of planarizing a semiconductor topography using multiple polish pads
Grant 5,968,843 - Dawson , et al. October 19, 1 | 1999-10-19 |
MOSFET device with an amorphized source
Grant 5,969,407 - Gardner , et al. October 19, 1 | 1999-10-19 |
Dissolvable dielectric method
Grant 5,953,626 - Hause , et al. September 14, 1 | 1999-09-14 |
Trench isolation structure having low K dielectric spacers arranged upon an oxide liner incorporated with nitrogen
Grant 5,943,585 - May , et al. August 24, 1 | 1999-08-24 |
Method of processing a semiconductor wafer for controlling drive current
Grant 5,943,550 - Fulford, Jr. , et al. August 24, 1 | 1999-08-24 |
Method for forming an IGFET with silicide source/drain contacts in close proximity to a gate with sloped sidewalls
Grant 5,937,299 - Michael , et al. August 10, 1 | 1999-08-10 |
Method of making an IGFET with a multilevel gate
Grant 5,930,634 - Hause , et al. July 27, 1 | 1999-07-27 |
Transistor with buried insulative layer beneath the channel region
Grant 5,930,642 - Moore , et al. July 27, 1 | 1999-07-27 |
Method for achieving global planarization by forming minimum mesas in large field areas
Grant 5,926,713 - Hause , et al. July 20, 1 | 1999-07-20 |
Detached drain MOSFET
Grant 5,926,714 - Gardner , et al. July 20, 1 | 1999-07-20 |
Method of making an integrated circuit with oxidizable trench liner
Grant 5,926,717 - Michael , et al. July 20, 1 | 1999-07-20 |
Trench transistor with localized source/drain regions implanted through voids in trench
Grant 5,923,980 - Gardner , et al. July 13, 1 | 1999-07-13 |
Integrated circuit gate conductor having a gate dielectric which is substantially resistant to hot carrier effects
Grant 5,923,983 - Fulford, Jr. , et al. July 13, 1 | 1999-07-13 |
Method of reducing transistor channel length with oxidation inhibiting spacers
Grant 5,918,134 - Gardner , et al. June 29, 1 | 1999-06-29 |
Method of fabricating an integrated circuit having devices arranged with different device densities using a bias differential to form devices with a uniform size
Grant 5,918,126 - Fulford, Jr. , et al. June 29, 1 | 1999-06-29 |
Method of channel doping using diffusion from implanted polysilicon
Grant 5,918,129 - Fulford, Jr. , et al. June 29, 1 | 1999-06-29 |
Process of using electrical signals for determining lithographic misalignment of vias relative to electrically active elements
Grant 5,916,715 - Fulford, Jr. , et al. June 29, 1 | 1999-06-29 |
Ion implantation process to improve the gate oxide quality at the edge of a shallow trench isolation structure
Grant 5,915,195 - Fulford, Jr. , et al. June 22, 1 | 1999-06-22 |
Method of implanting silicon through a polysilicon gate for punchthrough control of a semiconductor device
Grant 5,899,732 - Gardner , et al. May 4, 1 | 1999-05-04 |
Ultra-short transistor fabrication scheme for enhanced reliability
Grant 5,900,666 - Gardner , et al. May 4, 1 | 1999-05-04 |
Selective spacer formation for optimized silicon area reduction
Grant 5,898,202 - Fulford, Jr. , et al. April 27, 1 | 1999-04-27 |
MOS transistor employing a removable, dual layer etch stop to protect implant regions from sidewall spacer overetch
Grant 5,895,955 - Gardner , et al. April 20, 1 | 1999-04-20 |
Trench transistor with localized source/drain regions implanted through selectively grown oxide layer
Grant 5,888,880 - Gardner , et al. March 30, 1 | 1999-03-30 |
Composite gate electrode incorporating dopant diffusion-retarding barrier layer adjacent to underlying gate dielectric
Grant 5,885,877 - Gardner , et al. March 23, 1 | 1999-03-23 |
Method of making an igfet with selectively doped multilevel polysilicon gate
Grant 5,885,887 - Hause , et al. March 23, 1 | 1999-03-23 |
Method for forming an integrated circuit having transistors of dissimilarly graded junction profiles
Grant 5,882,973 - Gardner , et al. March 16, 1 | 1999-03-16 |
High-performance PMOS transistor using a barrier implant in the source-side of the transistor channel
Grant 5,882,974 - Gardner , et al. March 16, 1 | 1999-03-16 |
Method of forming an insulated-gate field-effect transistor with metal spacers
Grant 5,877,058 - Gardner , et al. March 2, 1 | 1999-03-02 |
Method of making N-channel and P-channel devices using two tube anneals and two rapid thermal anneals
Grant 5,877,050 - Gardner , et al. March 2, 1 | 1999-03-02 |
CMOS integrated circuit and method for forming source/drain areas prior to forming lightly doped drains to optimize the thermal diffusivity thereof
Grant 5,874,343 - Fulford, Jr. , et al. February 23, 1 | 1999-02-23 |
Subtrench conductor formation with large tilt angle implant
Grant 5,874,346 - Fulford Jr. , et al. February 23, 1 | 1999-02-23 |
Nitrogenated gate structure for improved transistor performance and method for making same
Grant 5,872,049 - Gardner , et al. February 16, 1 | 1999-02-16 |
Integrated circuit having sacrificial spacers for producing graded NMOS source/drain junctions possibly dissimilar from PMOS source/drain junctions
Grant 5,869,866 - Fulford, Jr. , et al. February 9, 1 | 1999-02-09 |
CMOS integrated circuit having a sacrificial metal spacer for producing graded NMOS source/drain junctions dissimilar from PMOS source/drain junctions
Grant 5,869,879 - Fulford, Jr. , et al. February 9, 1 | 1999-02-09 |
Integrated circuit having horizontally and vertically offset interconnect lines
Grant 5,854,131 - Dawson , et al. December 29, 1 | 1998-12-29 |
Method for forming a multilevel interconnect structure of an integrated circuit by a single via etch and single fill process
Grant 5,851,913 - Brennan , et al. December 22, 1 | 1998-12-22 |
Method of making transistor having a gate dielectric which is substantially resistant to drain-side hot carrier injection
Grant 5,851,893 - Gardner , et al. December 22, 1 | 1998-12-22 |
IGFET method of forming with silicide contact on ultra-thin gate
Grant 5,851,891 - Dawson , et al. December 22, 1 | 1998-12-22 |
Substantially planar semiconductor topography using dielectrics and chemical mechanical polish
Grant 5,850,105 - Dawson , et al. December 15, 1 | 1998-12-15 |
Integrated circuit gate conductor which uses layered spacers to produce a graded junction
Grant 5,847,428 - Fulford, Jr. , et al. December 8, 1 | 1998-12-08 |
Integrated circuit having conductors of enhanced cross-sectional area with etch stop barrier layer
Grant 5,847,462 - Bandyopadhyay , et al. December 8, 1 | 1998-12-08 |
Integrated circuit which uses a damascene process for producing staggered interconnect lines
Grant 5,846,876 - Bandyopadhyay , et al. December 8, 1 | 1998-12-08 |
CMOS integrated circuit and method for implanting NMOS transistor areas prior to implanting PMOS transistor areas to optimize the thermal diffusivity thereof
Grant 5,844,276 - Fulford, Jr. , et al. December 1, 1 | 1998-12-01 |
Individually controllable radiation sources for providing an image pattern in a photolithographic system
Grant 5,840,451 - Moore , et al. November 24, 1 | 1998-11-24 |
CMOS integrated circuit formed by using removable spacers to produce asymmetrical NMOS junctions before asymmetrical PMOS junctions for optimizing thermal diffusivity of dopants implanted therein
Grant 5,837,572 - Gardner , et al. November 17, 1 | 1998-11-17 |
Asymmetrical transistor with lightly doped drain region, heavily doped source and drain regions, and ultra-heavily doped source region
Grant 5,831,306 - Gardner , et al. November 3, 1 | 1998-11-03 |
Method of making NMOS and devices with sequentially formed gates having different gate lengths
Grant 5,827,761 - Fulford, Jr. , et al. October 27, 1 | 1998-10-27 |
Method of making an integrated circuit which uses an etch stop for producing staggered interconnect lines
Grant 5,827,776 - Bandyopadhyay , et al. October 27, 1 | 1998-10-27 |
Interlevel dielectric with air gaps to lessen capacitive coupling
Grant 5,814,555 - Bandyopadhyay , et al. September 29, 1 | 1998-09-29 |
Non-volatile memory device having a floating gate with enhanced charge retention
Grant 5,805,013 - Ghneim , et al. September 8, 1 | 1998-09-08 |
Selectively doped channel region for increased I.sub.Dsat and method for making same
Grant 5,804,497 - Gardner , et al. September 8, 1 | 1998-09-08 |
Method of forming a gate electrode for an IGFET
Grant 5,801,088 - Gardner , et al. September 1, 1 | 1998-09-01 |
Method of forming trench transistor with metal spacers
Grant 5,801,075 - Gardner , et al. September 1, 1 | 1998-09-01 |
Method of making non-volatile memory device having a floating gate with enhanced charge retention
Grant 5,801,076 - Ghneim , et al. September 1, 1 | 1998-09-01 |
Trench transistor in combination with trench array
Grant 5,796,143 - Fulford, Jr. , et al. August 18, 1 | 1998-08-18 |
Interlevel dielectric with air gaps to reduce permitivity
Grant 5,792,706 - Michael , et al. August 11, 1 | 1998-08-11 |
Integrated circuit having multiple LDD and/or source/drain implant steps to enhance circuit performance
Grant 5,793,090 - Gardner , et al. August 11, 1 | 1998-08-11 |
Method of making IGFETs in densely and sparsely populated areas of a substrate
Grant 5,789,300 - Fulford, Jr. August 4, 1 | 1998-08-04 |
Transistor with source and drain regions within the semiconductor substrate detached or laterally displaced from the transistor gate
Grant 5,789,780 - Fulford, Jr. , et al. August 4, 1 | 1998-08-04 |
Method of reducing MOS transistor gate beyond photolithographically patterned dimension
Grant 5,786,256 - Gardner , et al. July 28, 1 | 1998-07-28 |
Semiconductor interlevel dielectric having a polymide for producing air gaps
Grant 5,783,481 - Brennan , et al. July 21, 1 | 1998-07-21 |
Multilevel interconnect structure of an integrated circuit having air gaps and pillars separating levels of interconnect
Grant 5,783,864 - Dawson , et al. July 21, 1 | 1998-07-21 |
MOSFET device with an amorphized source and fabrication method thereof
Grant 5,770,485 - Gardner , et al. June 23, 1 | 1998-06-23 |
Method of forming a recessed interconnect structure
Grant 5,767,012 - Fulford, Jr. , et al. June 16, 1 | 1998-06-16 |
Method of formation of an air gap within a semiconductor dielectric by solvent desorption
Grant 5,759,913 - Fulford, Jr. , et al. June 2, 1 | 1998-06-02 |
Inspection of lens error associated with lens heating in a photolithographic system
Grant 5,723,238 - Moore , et al. March 3, 1 | 1998-03-03 |
Method of forming a shallow junction by diffusion from a silicon-based spacer
Grant 5,710,054 - Gardner , et al. January 20, 1 | 1998-01-20 |
Method for achieving a highly reliable oxide film
Grant 5,591,681 - Wristers , et al. January 7, 1 | 1997-01-07 |
Method for fabricating thin oxides for a semiconductor technology
Grant 5,498,577 - Fulford, Jr. , et al. March 12, 1 | 1996-03-12 |
Semiconductor wafer with enhanced pre-process denudation and process-induced gettering
Grant 5,445,975 - Gardner , et al. August 29, 1 | 1995-08-29 |
| 