| Patent | Date |
|---|
Three-dimensional Device With Vertical Core And Bundled Wiring
App 20220293523 - Gardner; Mark I. ; et al. | 2022-09-15 |
3d Device With A Plurality Of Core Wiring Layout Architecture
App 20220293789 - Fulford; H. Jim ; et al. | 2022-09-15 |
High Density Logic Formation Using Multi-dimensional Laser Annealing
App 20220277957 - Fulford; H. Jim ; et al. | 2022-09-01 |
3d Devices With 3d Diffusion Breaks And Method Of Forming The Same
App 20220254690 - FULFORD; H. Jim ; et al. | 2022-08-11 |
3d Devices With 3d Diffusion Breaks And Method Of Forming The Same
App 20220254925 - GARDNER; Mark I. ; et al. | 2022-08-11 |
Method Of Making Vertical Semiconductor Nanosheets With Diffusion Breaks
App 20220254689 - GARDNER; Mark I. ; et al. | 2022-08-11 |
Method of making 3D CMOS with integrated channel and S/D regions
Grant 11,410,888 - Gardner , et al. August 9, 2 | 2022-08-09 |
3D semiconductor apparatus manufactured with a cantilever structure and method of manufacture thereof
Grant 11,410,992 - Fulford , et al. August 9, 2 | 2022-08-09 |
Multiple Nano Layer Transistor Layers With Different Transistor Architectures For Improved Circuit Layout And Performance
App 20220246612 - FULFORD; H. Jim ; et al. | 2022-08-04 |
Localized Stress Regions For Three-dimension Chiplet Formation
App 20220238328 - DEVILLIERS; Anton J. ; et al. | 2022-07-28 |
Method To Enhance 3d Horizontal Nanosheets Device Performance
App 20220238520 - GARDNER; Mark I. ; et al. | 2022-07-28 |
High Performance 3d Vertical Transistor Device Enhancement Design
App 20220238652 - GARDNER; Mark I. ; et al. | 2022-07-28 |
Localized Stress Regions For Three-dimension Chiplet Formation
App 20220238380 - DEVILLIERS; Anton J. ; et al. | 2022-07-28 |
Method of architecture design for enhanced 3D device performance
Grant 11,393,813 - Gardner , et al. July 19, 2 | 2022-07-19 |
Multiple nano layer transistor layers with different transistor architectures for improved circuit layout and performance
Grant 11,362,091 - Fulford , et al. June 14, 2 | 2022-06-14 |
High Density Architecture Design For 3d Logic And 3d Memory Circuits
App 20220181315 - Gardner; Mark I. ; et al. | 2022-06-09 |
Method of making six transistor SRAM cell using connections between 3D transistor stacks
Grant 11,342,339 - Gardner , et al. May 24, 2 | 2022-05-24 |
Method For Threshold Voltage Tuning Through Selective Deposition Of High-k Metal Gate (hkmg) Film Stacks
App 20220148924 - SMITH; Jeffrey ; et al. | 2022-05-12 |
Method For Designing Three Dimensional Metal Lines For Enhanced Device Performance
App 20220139783 - Gardner; Mark I. ; et al. | 2022-05-05 |
High Precision 3d Metal Stacking For A Plurality Of 3d Devices
App 20220139786 - GARDNER; Mark I. ; et al. | 2022-05-05 |
High Density 3d Layout Enhancement Of Multiple Cmos Devices
App 20220140112 - FULFORD; H. Jim ; et al. | 2022-05-05 |
Method Of Making 3d Circuits With Integrated Stacked 3d Metal Lines For High Density Circuits
App 20220115271 - GARDNER; Mark I. ; et al. | 2022-04-14 |
Method for fabricating a 3D semiconductor apparatus having two vertically disposed seminconductor devices
Grant 11,302,587 - Gardner , et al. April 12, 2 | 2022-04-12 |
Three-dimensional Universal Cmos Device
App 20220102492 - Gardner; Mark I. ; et al. | 2022-03-31 |
Method Of Making A Plurality Of High Density Logic Elements With Advanced Cmos Device Layout
App 20220102533 - GARDNER; Mark I. ; et al. | 2022-03-31 |
High Performance Floating Body Vfet With Dielectric Core
App 20220102552 - FULFORD; H. Jim ; et al. | 2022-03-31 |
Plurality Of 3d Vertical Cmos Devices For High Performance Logic
App 20220102345 - GARDNER; Mark I. ; et al. | 2022-03-31 |
High density architecture design for 3D logic and 3D memory circuits
Grant 11,282,828 - Gardner , et al. March 22, 2 | 2022-03-22 |
Device and method of forming with three-dimensional memory and three-dimensional logic
Grant 11,276,704 - Gardner , et al. March 15, 2 | 2022-03-15 |
Method For Fabricating A 3d Semiconductor Apparatus Having Two Vertically Disposed Seminconductor Devices
App 20220077003 - GARDNER; Mark I. ; et al. | 2022-03-10 |
Method for threshold voltage tuning through selective deposition of high-K metal gate (HKMG) film stacks
Grant 11,264,289 - Smith , et al. March 1, 2 | 2022-03-01 |
Optimum High Density 3d Device Layout And Method Of Fabrication
App 20220059413 - GARDNER; Mark I. ; et al. | 2022-02-24 |
Multiple Planes Of Transistors With Different Transistor Architectures To Enhance 3d Logic And Memory Circuits
App 20220052186 - GARDNER; Mark I. ; et al. | 2022-02-17 |
Formation Of Low-temperature And High-temperature In-situ Doped Source And Drain Epitaxy Using Selective Heating For Wrap-around Contact And Vertically Stacked Device Architectures
App 20220051905 - SMITH; Jeffrey ; et al. | 2022-02-17 |
Method of making 3D circuits with integrated stacked 3D metal lines for high density circuits
Grant 11,251,080 - Gardner , et al. February 15, 2 | 2022-02-15 |
High performance CMOS using 3D device layout
Grant 11,251,159 - Fulford , et al. February 15, 2 | 2022-02-15 |
High Performance Nanosheet Fabrication Method With Enhanced High Mobility Channel Elements
App 20220020744 - Gardner; Mark I. ; et al. | 2022-01-20 |
Multiple planes of transistors with different transistor architectures to enhance 3D logic and memory circuits
Grant 11,222,964 - Gardner , et al. January 11, 2 | 2022-01-11 |
3d Semiconductor Apparatus Manufactured With A Cantilever Structure And Method Of Manufacture Thereof
App 20220005805 - FULFORD; H. Jim ; et al. | 2022-01-06 |
Method Of Making 3d Isolation
App 20210391207 - GARDNER; Mark I. ; et al. | 2021-12-16 |
High performance nanosheet fabrication method with enhanced high mobility channel elements
Grant 11,195,832 - Gardner , et al. December 7, 2 | 2021-12-07 |
Method Of Architecture Design For Enhanced 3d Device Performance
App 20210366904 - GARDNER; Mark I. ; et al. | 2021-11-25 |
Metal Connections And Routing For Advanced 3d Layout Designs
App 20210366787 - FULFORD; H. Jim ; et al. | 2021-11-25 |
Method for fabrication of high density logic and memory for advanced circuit architecture
Grant 11,177,250 - Gardner , et al. November 16, 2 | 2021-11-16 |
Method Of Making Multiple Nano Layer Transistors To Enhance A Multiple Stack Cfet Performance
App 20210351180 - Fulford; H. Jim ; et al. | 2021-11-11 |
Method For Die-level Unique Authentication And Serialization Of Semiconductor Devices Using Electrical And Optical Marking
App 20210351053 - FULFORD; H. Jim ; et al. | 2021-11-11 |
High performance circuit applications using stacked 3D metal lines
Grant 11,171,208 - Fulford , et al. November 9, 2 | 2021-11-09 |
Method Of Expanding 3d Device Architectural Designs For Enhanced Performance
App 20210343857 - GARDNER; Mark I. ; et al. | 2021-11-04 |
High Performance Multi-dimensional Device And Logic Integration
App 20210343714 - GARDNER; Mark I. ; et al. | 2021-11-04 |
Unified Architectural Design For Enhanced 3d Circuit Options
App 20210313327 - GARDNER; Mark I. ; et al. | 2021-10-07 |
Method of making 3D source drains with hybrid stacking for optimum 3D logic layout
Grant 11,139,213 - Gardner , et al. October 5, 2 | 2021-10-05 |
Method for die-level unique authentication and serialization of semiconductor devices using electrical and optical marking
Grant 11,133,206 - Fulford , et al. September 28, 2 | 2021-09-28 |
Method of making multiple nano layer transistors to enhance a multiple stack CFET performance
Grant 11,133,310 - Fulford , et al. September 28, 2 | 2021-09-28 |
Horizontal Programmable Conducting Bridges Between Conductive Lines
App 20210287980 - Fulford; H. Jim ; et al. | 2021-09-16 |
High density logic formation using multi-dimensional laser annealing
Grant 11,114,346 - Fulford , et al. September 7, 2 | 2021-09-07 |
Multi-dimensional planes of logic and memory formation using single crystal silicon orientations
Grant 11,107,733 - Gardner , et al. August 31, 2 | 2021-08-31 |
Split Substrate Interposer With Integrated Passive Device
App 20210265253 - BHATTACHERJEE; Arya ; et al. | 2021-08-26 |
High Density Architecture Design For 3d Logic And 3d Memory Circuits
App 20210265333 - Gardner; Mark I. ; et al. | 2021-08-26 |
Split Substrate Interposer
App 20210265254 - BHATTACHERJEE; Arya ; et al. | 2021-08-26 |
Architecture Design And Process For 3d Logic And 3d Memory
App 20210249430 - Fulford; H. Jim ; et al. | 2021-08-12 |
Efficient Three-dimensional Design For Logic Applications Using Variable Voltage Threshold Three-dimensional Cmos Devices
App 20210242351 - GARDNER; MARK I. ; et al. | 2021-08-05 |
Horizontal programmable conducting bridges between conductive lines
Grant 11,069,616 - Fulford , et al. July 20, 2 | 2021-07-20 |
Method Of Making A Continuous Channel Between 3d Cmos
App 20210217666 - FULFORD; H. Jim ; et al. | 2021-07-15 |
3d Complementary Metal Oxide Semiconductor (cmos) Device And Method Of Forming The Same
App 20210202481 - FULFORD; H. Jim ; et al. | 2021-07-01 |
Method Of Making Six Transistor Sram Cell Using Connections Between 3d Transistor Stacks
App 20210202499 - GARDNER; Mark I. ; et al. | 2021-07-01 |
Method Of Making 3d Cmos With Integrated Channel And S/d Regions
App 20210175128 - GARDNER; Mark I. ; et al. | 2021-06-10 |
High Performance Cmos Using 3d Device Layout
App 20210175209 - FULFORD; H. Jim ; et al. | 2021-06-10 |
High Performance Circuit Applications Using Stacked 3d Metal Lines
App 20210175327 - FULFORD; H. Jim ; et al. | 2021-06-10 |
3d Semiconductor Apparatus Manufactured With A Plurality Of Substrates And Method Of Manufacture Thereof
App 20210175358 - GARDNER; Mark I. ; et al. | 2021-06-10 |
Method Of Making 3d Circuits With Integrated Stacked 3d Metal Lines For High Density Circuits
App 20210166975 - GARDNER; Mark I. ; et al. | 2021-06-03 |
Method Of Making 3d Source Drains With Hybrid Stacking For Optimum 3d Logic Layout
App 20210143065 - GARDNER; Mark I. ; et al. | 2021-05-13 |
Method Of Making A Charge Trap Tfet Semiconductor Device For Advanced Logic Operations
App 20210118879 - GARDNER; Mark I. ; et al. | 2021-04-22 |
Device And Method Of Forming With Three-dimensional Memory And Three-dimensional Logic
App 20210111183 - Gardner; Mark I. ; et al. | 2021-04-15 |
Device And Method Of Forming With Three-dimensional Memory And Three-dimensional Logic
App 20210111258 - Fulford; H. Jim ; et al. | 2021-04-15 |
Method Of Making Multiple Nano Layer Transistors To Enhance A Multiple Stack Cfet Performance
App 20210104523 - Fulford; H. Jim ; et al. | 2021-04-08 |
High Performance Nanosheet Fabrication Method With Enhanced High Mobility Channel Elements
App 20210104522 - Gardner; Mark I. ; et al. | 2021-04-08 |
Method For Fabrication Of High Density Logic And Memory For Advanced Circuit Architecture
App 20210082901 - GARDNER; Mark I. ; et al. | 2021-03-18 |
High Density Logic Formation Using Multi-dimensional Laser Annealing
App 20210043519 - FULFORD; H. Jim ; et al. | 2021-02-11 |
Multi-dimensional Planes Of Logic And Memory Formation Using Single Crystal Silicon Orientations
App 20210043516 - GARDNER; Mark I. ; et al. | 2021-02-11 |
Multiple Planes Of Transistors With Different Transistor Architectures To Enhance 3d Logic And Memory Circuits
App 20210013326 - Gardner; Mark I. ; et al. | 2021-01-14 |
Method For Threshold Voltage Tuning Through Selective Deposition Of High-k Metal Gate (hkmg) Film Stacks
App 20210013111 - SMITH; Jeffrey ; et al. | 2021-01-14 |
Multiple Nano Layer Transistor Layers With Different Transistor Architectures For Improved Circuit Layout And Performance
App 20200411518 - FULFORD; H. Jim ; et al. | 2020-12-31 |
Programmable Connection Segment And Method Of Forming The Same
App 20200365511 - Gardner; Mark I. ; et al. | 2020-11-19 |
Horizontal Programmable Conducting Bridges Between Conductive Lines
App 20200365507 - Fulford; H. Jim ; et al. | 2020-11-19 |
Multi-dimensional Vertical Switching Connections For Connecting Circuit Elements
App 20200365506 - Gardner; Mark I. ; et al. | 2020-11-19 |
Method For Die-level Unique Authentication And Serialization Of Semiconductor Devices Using Electrical And Optical Marking
App 20200328103 - FULFORD; H. Jim ; et al. | 2020-10-15 |
Method For Die-level Unique Authentication And Serialization Of Semiconductor Devices
App 20200328102 - SCHEPIS; Anthony ; et al. | 2020-10-15 |
Integrated circuit devices and methods of forming memory array and peripheral circuitry isolation
Grant 8,575,716 - Mathew , et al. November 5, 2 | 2013-11-05 |
Integrated Circuit Devices And Methods Of Forming Memory Array And Peripheral Circuitry Isolation
App 20130249050 - Mathew; James ; et al. | 2013-09-26 |
Integrated circuit devices and methods of forming memory array and peripheral circuitry isolation
Grant 8,461,016 - Mathew , et al. June 11, 2 | 2013-06-11 |
Integrated Circuit Devices And Methods Of Forming Memory Array And Peripheral Circuitry Isolation
App 20130087883 - Mathew; James ; et al. | 2013-04-11 |
Isolation structure having implanted silicon atoms at the top corner of the isolation trench filling vacancies and interstitial sites
Grant 6,979,878 - Gardner , et al. December 27, 2 | 2005-12-27 |
Method and apparatus for providing etch uniformity using zoned temperature control
Grant 6,746,616 - Fulford , et al. June 8, 2 | 2004-06-08 |
Method of controlling sheet resistance of metal silicide regions by controlling the salicide strip time
Grant 6,706,631 - Fulford March 16, 2 | 2004-03-16 |
Semiconductor device having large-area silicide layer and process of fabrication thereof
Grant 6,603,180 - Gardner , et al. August 5, 2 | 2003-08-05 |
Run-to-run etch control by feeding forward measured metal thickness
Grant 6,500,681 - Christian , et al. December 31, 2 | 2002-12-31 |
Asymmetrical transistor having a barrier-incorporated gate oxide and a graded implant only in the drain-side junction area
Grant 6,483,157 - Gardner , et al. November 19, 2 | 2002-11-19 |
Apparatus for filling trenches
Grant 6,454,899 - Campbell , et al. September 24, 2 | 2002-09-24 |
Transistor and a method for forming the transistor with elevated and/or relatively shallow source/drain regions to achieve enhanced gate electrode formation
Grant 6,355,955 - Gardner , et al. March 12, 2 | 2002-03-12 |
Method Of Making Ultra Thin Oxide Formation Using Selective Etchback Technique Integrated With Thin Nitride Layer For High Performance Mosfet
App 20020022325 - GARDNER, MARK I. ; et al. | 2002-02-21 |
Method of making a semiconductor device with self-aligned active, lightly-doped drain, and halo regions
Grant 6,300,205 - Fulford , et al. October 9, 2 | 2001-10-09 |
Semiconductor device having ultra shallow junctions and a reduced channel length and method for making same
Grant 6,261,909 - Gardner , et al. July 17, 2 | 2001-07-17 |
Method for forming a retrograde impurity profile
Grant 6,245,649 - Buller , et al. June 12, 2 | 2001-06-12 |
Method of forming ultra thin gate dielectric for high performance semiconductor devices
Grant 6,245,652 - Gardner , et al. June 12, 2 | 2001-06-12 |
Integrated circuit incorporating a memory cell and a transistor elevated above an insulating base
Grant 6,225,646 - Gardner , et al. May 1, 2 | 2001-05-01 |
Semiconductor device having metal gate electrode and titanium or tantalum nitride gate dielectric barrier layer and process of fabrication thereof
Grant 6,225,168 - Gardner , et al. May 1, 2 | 2001-05-01 |
Salicide and gate dielectric formed from a single layer of refractory metal
Grant 6,222,240 - Gardner , et al. April 24, 2 | 2001-04-24 |
High K integration of gate dielectric with integrated spacer formation for high speed CMOS
Grant 6,207,995 - Gardner , et al. March 27, 2 | 2001-03-27 |
Method of fabricating a transistor with a dielectric underlayer and device incorporating same
Grant 6,162,688 - Gardner , et al. December 19, 2 | 2000-12-19 |
Semiconductor device with asymmetric PMOS source/drain implant and method of manufacture thereof
Grant 6,146,934 - Gardner , et al. November 14, 2 | 2000-11-14 |
Semiconductor device having self-aligned asymmetric source/drain regions and method of fabrication thereof
Grant 6,146,952 - Nariman , et al. November 14, 2 | 2000-11-14 |
Adjusting the size of conductive lines based upon contact size
Grant 6,124,197 - Fulford September 26, 2 | 2000-09-26 |
Semiconductor device with vertical halo region and methods of manufacture
Grant 6,114,211 - Fulford , et al. September 5, 2 | 2000-09-05 |
Method of making disposable channel masking for both source/drain and LDD implant and subsequent gate fabrication
Grant 6,103,559 - Gardner , et al. August 15, 2 | 2000-08-15 |
Process for making high performance MOSFET with scaled gate electrode thickness
Grant 6,090,676 - Gardner , et al. July 18, 2 | 2000-07-18 |
V-gate transistor
Grant 6,078,078 - Gardner , et al. June 20, 2 | 2000-06-20 |
Complementary metal-oxide semiconductor device having source/drain regions formed using multiple spacers
Grant 6,074,906 - Cheek , et al. June 13, 2 | 2000-06-13 |
Semiconductor device having gate electrodes with different gate insulators and fabrication thereof
Grant 6,064,102 - Gardner , et al. May 16, 2 | 2000-05-16 |
Semiconductor device having a tri-layer gate insulating dielectric
Grant 6,057,584 - Gardner , et al. May 2, 2 | 2000-05-02 |
Semiconductor device fabrication using a sacrificial plug for defining a region for a gate electrode
Grant 6,051,487 - Gardner , et al. April 18, 2 | 2000-04-18 |
Method of making gate dielectric for sub-half micron MOS transistors including a graded dielectric constant
Grant 6,015,739 - Gardner , et al. January 18, 2 | 2000-01-18 |
Semiconductor device having a PMOS device with a source/drain region formed using a heavy atom p-type implant and method of manufacture thereof
Grant 6,013,546 - Gardner , et al. January 11, 2 | 2000-01-11 |
Short channel length MOSFET transistor
Grant 6,011,290 - Gardner , et al. January 4, 2 | 2000-01-04 |
Process for formation of isolation trenches with high-K gate dielectrics
Grant 6,008,095 - Gardner , et al. December 28, 1 | 1999-12-28 |
Method and apparatus for high performance transistor devices
Grant 5,981,363 - Gardner , et al. November 9, 1 | 1999-11-09 |
Method of making a self-aligned disposable gate electrode for advanced CMOS design
Grant 5,976,924 - Gardner , et al. November 2, 1 | 1999-11-02 |
Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor
Grant 5,959,333 - Gardner , et al. September 28, 1 | 1999-09-28 |
Resistance to gate dielectric breakdown at the edges of shallow trench isolation structures
Grant 5,930,620 - Wristers , et al. July 27, 1 | 1999-07-27 |
Asymmetrical transistor having a gate dielectric which is substantially resistant to hot carrier injection
Grant 5,920,103 - Fulford , et al. July 6, 1 | 1999-07-06 |
Semiconductor fabrication employing implantation of excess atoms at the edges of a trench isolation structure
Grant 5,891,787 - Gardner , et al. April 6, 1 | 1999-04-06 |
Reduction of dopant diffusion by the co-implantation of impurities into the transistor gate conductor
Grant 5,885,861 - Gardner , et al. March 23, 1 | 1999-03-23 |
Method of forming high pressure silicon oxynitride gate dielectrics
Grant 5,674,788 - Wristers , et al. October 7, 1 | 1997-10-07 |
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