loadpatents
name:-0.029961824417114
name:-0.037020921707153
name:-0.0016379356384277
Fu; Chu-Yun Patent Filings

Fu; Chu-Yun

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fu; Chu-Yun.The latest application filed is for "method of fabricating semiconductor device isolation structure".

Company Profile
2.44.30
  • Fu; Chu-Yun - Hsinchu TW
  • Fu; Chu-Yun - Hsin-Chu TW
  • FU; Chu-Yun - Hsinchu City TW
  • Fu; Chu-Yun - Taipei N/A TW
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method of fabricating semiconductor device isolation structure
Grant 10,269,616 - Yu , et al.
2019-04-23
Method of Fabricating Semiconductor Device Isolation Structure
App 20170330791 - Yu; Chen-Hua ;   et al.
2017-11-16
Fin field effect transistor
Grant 9,716,091 - Lin , et al. July 25, 2
2017-07-25
Method of fabricating semiconductor device isolation structure
Grant 9,673,082 - Yu , et al. June 6, 2
2017-06-06
Fin Field Effect Transistor
App 20160379977 - LIN; Hung-Ta ;   et al.
2016-12-29
Fin field effect transistor
Grant 9,379,215 - Lin , et al. June 28, 2
2016-06-28
Method of Fabricating Semiconductor Device Isolation Structure
App 20160133506 - Yu; Chen-Hua ;   et al.
2016-05-12
Fin Field Effect Transistor
App 20160087079 - Lin; Hung-Ta ;   et al.
2016-03-24
Method of fabricating semiconductor device isolation structure
Grant 9,224,606 - Yu , et al. December 29, 2
2015-12-29
Fin field effect transistor
Grant 9,209,300 - Lin , et al. December 8, 2
2015-12-08
Method of fabrication of a FinFET element
Grant 8,883,597 - Chang , et al. November 11, 2
2014-11-11
Fin Field Effect Transistor
App 20140327091 - LIN; Hung-Ta ;   et al.
2014-11-06
Self-aligned halo/pocket implantation for reducing leakage and source/drain resistance in MOS devices
Grant 8,822,293 - Yu , et al. September 2, 2
2014-09-02
Fin held effect transistor
Grant 8,809,940 - Lin , et al. August 19, 2
2014-08-19
Method for fabricating an isolation structure
Grant 8,580,653 - Lee , et al. November 12, 2
2013-11-12
Fin Field Effect Transistor
App 20130228865 - LIN; Hung-Ta ;   et al.
2013-09-05
Method For Fabricating An Isolation Structure
App 20130171803 - LEE; Tze-Liang ;   et al.
2013-07-04
FinFET and method of fabricating the same
Grant 8,440,517 - Lin , et al. May 14, 2
2013-05-14
Method for fabricating an isolation structure
Grant 8,404,561 - Lee , et al. March 26, 2
2013-03-26
Fabrication of source/drain extensions with ultra-shallow junctions
Grant 8,173,503 - Chiu , et al. May 8, 2
2012-05-08
Method of Fabricating Semiconductor Device Isolation Structure
App 20120094464 - Yu; Chen-Hua ;   et al.
2012-04-19
Finfet And Method Of Fabricating The Same
App 20120091538 - LIN; Hung-Ta ;   et al.
2012-04-19
Method of fabricating semiconductor device isolation structure
Grant 8,110,890 - Yu , et al. February 7, 2
2012-02-07
Polysilicon gate formation by in-situ doping
Grant 7,892,909 - Yu , et al. February 22, 2
2011-02-22
Method For Fabricating An Isolation Structure
App 20100291751 - LEE; Tze-Liang ;   et al.
2010-11-18
Fabrication of Source/Drain Extensions with Ultra-Shallow Junctions
App 20100216288 - Chiu; Yihang ;   et al.
2010-08-26
Fabrication of FinFETs with multiple fin heights
Grant 7,612,405 - Yu , et al. November 3, 2
2009-11-03
Method for forming a multi-layer shallow trench isolation structure in a semiconductor device
Grant 7,611,963 - Yang , et al. November 3, 2
2009-11-03
A Method For Forming A Multi-layer Shallow Trench Isolation Structure In A Semiconductor Device
App 20090267176 - Yang; Shu-Tine ;   et al.
2009-10-29
Self-Aligned Halo/Pocket Implantation for Reducing Leakage and Source/Drain Resistance in MOS Devices
App 20090233410 - Yu; Chen-Hua ;   et al.
2009-09-17
Method Of Fabrication Of A Finfet Element
App 20090035909 - Chang; Cheng-Hung ;   et al.
2009-02-05
Method of Fabricating Semiconductor Device Isolation Structure
App 20080303104 - Yu; Chen-Hua ;   et al.
2008-12-11
Polysilicon gate formation by in-situ doping
App 20080194072 - Yu; Chen-Hua ;   et al.
2008-08-14
Polysilicon gate formation by in-situ doping
App 20080194087 - Yu; Chen-Hua ;   et al.
2008-08-14
N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications
Grant 7,371,629 - Fu , et al. May 13, 2
2008-05-13
Scratch reduction for chemical mechanical polishing
Grant 7,297,632 - Hou , et al. November 20, 2
2007-11-20
Method of achieving improved STI gap fill with reduced stress
Grant 7,118,987 - Fu , et al. October 10, 2
2006-10-10
High performance strained channel MOSFETs by coupled stress effects
Grant 7,119,404 - Chang , et al. October 10, 2
2006-10-10
Scratch reduction for chemical mechanical polishing
App 20060211250 - Hou; Chuang-Ping ;   et al.
2006-09-21
Shallow trench isolation method for reducing oxide thickness variations at different pattern densities
Grant 7,098,116 - Lu , et al. August 29, 2
2006-08-29
System and method for contact module processing
App 20060157776 - Chang; Cheng-Hung ;   et al.
2006-07-20
Method and apparatus for real-time control and monitor of deposition processes
App 20060049036 - Chang; Cheng-Hung ;   et al.
2006-03-09
Selectively strained MOSFETs to improve drive current
App 20060024879 - Fu; Chu-Yun ;   et al.
2006-02-02
High performance strained channel mosfets by coupled stress effects
App 20050260806 - Chang, Cheng-Hung ;   et al.
2005-11-24
Method of achieving improved STI gap fill with reduced stress
App 20050170606 - Fu, Chu-Yun ;   et al.
2005-08-04
Novel shallow trench isolation method for reducing oxide thickness variations at different pattern densities
App 20050153519 - Lu, Chih-Cheng ;   et al.
2005-07-14
Test region layout for shallow trench isolation
App 20050095727 - Chang, Weng ;   et al.
2005-05-05
Method of forming contact plug on silicide structure
Grant 6,884,736 - Wu , et al. April 26, 2
2005-04-26
N/PMOS saturation current, HCE, and Vt stability by contact etch stop film modifications
App 20040110392 - Fu, Chu-Yun ;   et al.
2004-06-10
Method of forming contact plug on silicide structure
App 20040067635 - Wu, Chii-Ming ;   et al.
2004-04-08
Method for depositing dielectric materials onto semiconductor substrates by HDP (high density plasma) CVD (chemical vapor deposition) processes without damage to FET active devices
Grant 6,713,406 - Fu , et al. March 30, 2
2004-03-30
Borderless contact with buffer layer
Grant 6,630,398 - Tsai , et al. October 7, 2
2003-10-07
In situ dry etching procedure to form a borderless contact hole
Grant 6,497,993 - Chiu , et al. December 24, 2
2002-12-24
Borderless contact with buffer layer
App 20020192943 - Tsai, Ming Huan ;   et al.
2002-12-19
Interlevel dielectric composite layer for insulation of polysilicon and metal structures
Grant 6,479,385 - Jang , et al. November 12, 2
2002-11-12
Method of high density plasma phosphosilicate glass process on pre-metal dielectric application for plasma damage reducing and throughput improvement
Grant 6,461,966 - Chen , et al. October 8, 2
2002-10-08
Method to reduce STI HDP-CVD USG deposition induced defects
Grant 6,426,272 - Fu , et al. July 30, 2
2002-07-30
Crack resistant multi-layer dielectric layer and method for formation thereof
Grant 6,372,664 - Jang , et al. April 16, 2
2002-04-16
Integrated high density plasma chemical vapor deposition (HDP-CVD) method and chemical mechanical polish (CMP) planarizing method for forming patterned planarized aperture fill layers
Grant 6,365,523 - Jang , et al. April 2, 2
2002-04-02
High selectivity Si-rich SiON etch-stop layer
Grant 6,316,348 - Fu , et al. November 13, 2
2001-11-13
High selectivity Si-rich SiON etch-stop layer
App 20010034121 - Fu, Chu Yun ;   et al.
2001-10-25
High selectivity Si-rich SiON etch-stop layer
Grant 6,245,669 - Fu , et al. June 12, 2
2001-06-12
Removal of SiON ARC film after poly photo and etch
Grant 6,245,682 - Fu , et al. June 12, 2
2001-06-12
Shallow trench isolation methods employing gap filling doped silicon oxide dielectric layer
Grant 6,214,698 - Liaw , et al. April 10, 2
2001-04-10
Method of patterning narrow gate electrode
Grant 6,174,818 - Tao , et al. January 16, 2
2001-01-16
Chemical mechanical polish (CMP) planarizing trench fill method employing composite trench fill layer
Grant 6,090,714 - Jang , et al. July 18, 2
2000-07-18
Shallow trench isolation filled by high density plasma chemical vapor deposition
Grant 6,037,018 - Jang , et al. March 14, 2
2000-03-14

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