Fronheiser; Jody

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fronheiser; Jody.The latest application filed is for "field-effect transistors with a grown silicon-germanium channel".

Company Profile

4.15.18

Fronheiser; Jody - Delmar NY
Fronheiser; Jody - Albany NY
Fronheiser; Jody - Selkirk NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Field-effect transistors with a grown silicon-germanium channel Grant 10,680,065 - Mulfinger , et al.	2020-06-09
Surface area and Schottky barrier height engineering for contact trench epitaxy Grant 10,643,893 - Fronheiser , et al.	2020-05-05
Surface area and Schottky barrier height engineering for contact trench epitaxy Grant 10,643,894 - Fronheiser , et al.	2020-05-05
Field-effect Transistors With A Grown Silicon-germanium Channel App 20200044029 - Mulfinger; George R. ; et al.	2020-02-06
Semiconductor integrated structure having an epitaxial SiGe layer extending from silicon-containing regions formed between segments of oxide regions Grant 10,032,912 - Morin , et al. July 24, 2	2018-07-24
FORMING DEFECT-FREE RELAXED SiGe FINS App 20180130656 - Holt; Judson Robert ; et al.	2018-05-10
Forming defect-free relaxed SiGe fins Grant 9,882,052 - Holt , et al. January 30, 2	2018-01-30
Surface Area And Schottky Barrier Height Engineering For Contact Trench Epitaxy App 20180006141 - Fronheiser; Jody ; et al.	2018-01-04
Forming A Silicon Based Layer In A Trench To Prevent Corner Rounding App 20180005826 - JACOB; Ajey P. ; et al.	2018-01-04
Surface Area And Schottky Barrier Height Engineering For Contact Trench Epitaxy App 20180006140 - Fronheiser; Jody ; et al.	2018-01-04
Forming Defect-free Relaxed Sige Fins App 20180006155 - HOLT; Robert Judson ; et al.	2018-01-04
Thin strain relaxed buffers with multilayer film stacks Grant 9,679,972 - Fronheiser , et al. June 13, 2	2017-06-13
Early PTS with buffer for channel doping control Grant 9,647,086 - Bentley , et al. May 9, 2	2017-05-09
Methods of forming low defect replacement fins for a FinFET semiconductor device and the resulting devices Grant 9,614,058 - Fronheiser , et al. April 4, 2	2017-04-04
Early Pts With Buffer For Channel Doping Control App 20170047425 - BENTLEY; Steven ; et al.	2017-02-16
Self-aligned dual-height isolation for bulk FinFET Grant 9,564,486 - Akarvardar , et al. February 7, 2	2017-02-07
Defect-free Strain Relaxed Buffer Layer App 20160190304 - MORIN; Pierre ; et al.	2016-06-30
Self-aligned dual-height isolation for bulk FinFET Grant 9,324,790 - Akarvardar , et al. April 26, 2	2016-04-26
Methods Of Forming Metastable Replacement Fins For A Finfet Semiconductor Device By Performing A Replacement Growth Process App 20160064250 - Jacob; Ajey P. ; et al.	2016-03-03
Raised Source/drain Epi With Suppressed Lateral Epi Overgrowth App 20160056238 - LIM; Kwan-Yong ; et al.	2016-02-25
Methods of forming replacement fins for a FinFET semiconductor device by performing a replacement growth process Grant 9,240,342 - Jacob , et al. January 19, 2	2016-01-19
Methods Of Forming Low Defect Replacement Fins For A Finfet Semiconductor Device And The Resulting Devices App 20160013296 - Fronheiser; Jody ; et al.	2016-01-14
Raised source/drain EPI with suppressed lateral EPI overgrowth Grant 9,236,452 - Lim , et al. January 12, 2	2016-01-12
Self-aligned Dual-height Isolation For Bulk Finfet App 20150372080 - Akarvardar; Murat Kerem ; et al.	2015-12-24
Raised Source/drain Epi With Suppressed Lateral Epi Overgrowth App 20150340471 - LIM; Kwan-Yong ; et al.	2015-11-26
Method to form defect free replacement fins by H2 anneal Grant 9,165,837 - Fronheiser , et al. October 20, 2	2015-10-20
Self-aligned Dual-height Isolation For Bulk Finfet App 20150137308 - Akarvardar; Murat Kerem ; et al.	2015-05-21
Methods Of Forming Replacement Fins For A Finfet Semiconductor Device By Performing A Replacement Growth Process App 20150024573 - Jacob; Ajey P. ; et al.	2015-01-22
Methods Of Forming Low Defect Replacement Fins For A Finfet Semiconductor Device And The Resulting Devices App 20140264488 - Fronheiser; Jody ; et al.	2014-09-18
Methods for fabricating integrated circuits having confined epitaxial growth regions Grant 8,815,685 - LiCausi , et al. August 26, 2	2014-08-26
Methods For Fabricating Integrated Circuits Having Confined Epitaxial Growth Regions App 20140213037 - LiCausi; Nicholas ; et al.	2014-07-31
Methods of forming a three-dimensional semiconductor device with a nanowire channel structure Grant 8,728,885 - Pham , et al. May 20, 2	2014-05-20
Nano-devices And Methods Of Manufacture Thereof App 20100108132 - Tsakalakos; Loucas ; et al.	2010-05-06

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