| Patent | Date |
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Translation load instruction with access protection
Grant 11,226,902 - Williams , et al. January 18, 2 | 2022-01-18 |
Operation of a multi-slice processor implementing adaptive prefetch control
Grant 11,119,932 - Frey , et al. September 14, 2 | 2021-09-14 |
Translation Load Instruction
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Hardware-based pre-page walk virtual address transformation independent of page size utilizing bit shifting based on page size
Grant 10,956,340 - Bybell , et al. March 23, 2 | 2021-03-23 |
Interruptible translation entry invalidation in a multithreaded data processing system
Grant 10,817,434 - Williams , et al. October 27, 2 | 2020-10-27 |
Interruptible Translation Entry Invalidation In A Multithreaded Data Processing System
App 20200201780 - WILLIAMS; DEREK E. ; et al. | 2020-06-25 |
Efficient enforcement of barriers with respect to memory move sequences
Grant 10,613,792 - Frey , et al. | 2020-04-07 |
Hardware based isolation for secure execution of virtual machines
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Operation Of A Multi-slice Processor Implementing Adaptive Prefetch Control
App 20190213133 - FREY; BRADLY G. ; et al. | 2019-07-11 |
Operation of a multi-slice processor implementing adaptive prefetch control
Grant 10,331,566 - Frey , et al. | 2019-06-25 |
Hardware-based Pre-page Walk Virtual Address Transformation Independent Of Page Size Utilizing Bit Shifting Based On Page Size
App 20190188147 - Bybell; Anthony J. ; et al. | 2019-06-20 |
Hardware-based pre-page walk virtual address transformation where the virtual address is shifted by current page size and a minimum page size
Grant 10,216,642 - Bybell , et al. Feb | 2019-02-26 |
Hardware Based Isolation For Secure Execution Of Virtual Machines
App 20190034666 - Boivie; Richard H. ; et al. | 2019-01-31 |
Efficient Enforcement Of Barriers With Respect To Memory Move Sequences
App 20180373436 - FREY; BRADLY G. ; et al. | 2018-12-27 |
Memory move instruction sequence including a stream of copy-type and paste-type instructions
Grant 10,152,322 - Frey , et al. Dec | 2018-12-11 |
Efficient enforcement of barriers with respect to memory move sequences
Grant 10,067,713 - Frey , et al. September 4, 2 | 2018-09-04 |
Operation Of A Multi-slice Processor Implementing Adaptive Prefetch Control
App 20180157602 - FREY; BRADLY G. ; et al. | 2018-06-07 |
Efficient Enforcement Of Barriers With Respect To Memory Move Sequences
App 20180052606 - FREY; BRADLY G. ; et al. | 2018-02-22 |
Memory Move Instruction Sequence Including A Stream Of Copy-type And Paste-type Instructions
App 20180052687 - FREY; BRADLY G. ; et al. | 2018-02-22 |
Translation entry invalidation in a multithreaded data processing system
Grant 9,785,557 - Frey , et al. October 10, 2 | 2017-10-10 |
Translation entry invalidation in a multithreaded data processing system
Grant 9,772,945 - Frey , et al. September 26, 2 | 2017-09-26 |
Virtual unifed instruction and data caches including storing program instructions and memory address in CAM indicated by store instruction containing bit directly indicating self modifying code
Grant 9,747,212 - Chen, Jr. , et al. August 29, 2 | 2017-08-29 |
Determining failure context in hardware transactional memories
Grant 9,626,256 - Cain , et al. April 18, 2 | 2017-04-18 |
Transactional memory system supporting unbroken suspended execution
Grant 9,626,187 - Cain, III , et al. April 18, 2 | 2017-04-18 |
Selectable address translation mechanisms
Grant 9,600,419 - Bybell , et al. March 21, 2 | 2017-03-21 |
Push instruction for pushing a message payload from a sending thread to a receiving thread
Grant 9,575,825 - Arimilli , et al. February 21, 2 | 2017-02-21 |
Push instruction for pushing a message payload from a sending thread to a receiving thread
Grant 9,569,293 - Arimilli , et al. February 14, 2 | 2017-02-14 |
Interaction of transactional storage accesses with other atomic semantics
Grant 9,430,166 - Frey , et al. August 30, 2 | 2016-08-30 |
Rewind only transactions in a data processing system supporting transactional storage accesses
Grant 9,396,115 - Blainey , et al. July 19, 2 | 2016-07-19 |
Push Instruction For Pushing A Message Payload From A Sending Thread To A Receiving Thread
App 20160179591 - ARIMILLI; LAKSHMINARAYANA B. ; et al. | 2016-06-23 |
Push Instruction For Pushing A Message Payload From A Sending Thread To A Receiving Thread
App 20160179593 - ARIMILLI; LAKSHMINARAYANA B. ; et al. | 2016-06-23 |
Transaction check instruction for memory transactions
Grant 9,367,263 - Frey , et al. June 14, 2 | 2016-06-14 |
Transaction check instruction for memory transactions
Grant 9,367,264 - Frey , et al. June 14, 2 | 2016-06-14 |
Asymmetric co-existent address translation structure formats
Grant 9,348,763 - Bybell , et al. May 24, 2 | 2016-05-24 |
Nested rewind only and non rewind only transactions in a data processing system supporting transactional storage accesses
Grant 9,342,454 - Frey , et al. May 17, 2 | 2016-05-17 |
Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces
Grant 9,330,023 - Bybell , et al. May 3, 2 | 2016-05-03 |
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
Grant 9,323,692 - Bybell , et al. April 26, 2 | 2016-04-26 |
Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spaces
Grant 9,317,443 - Bybell , et al. April 19, 2 | 2016-04-19 |
Managing translation of a same address across multiple contexts using a same entry in a translation lookaside buffer
Grant 9,311,249 - Bybell , et al. April 12, 2 | 2016-04-12 |
Asymmetric co-existent address translation structure formats
Grant 9,280,488 - Bybell , et al. March 8, 2 | 2016-03-08 |
Recording and profiling transaction failure source addresses and states of validity indicator corresponding to addresses of aborted transaction in hardware transactional memories
Grant 9,268,598 - Blainey , et al. February 23, 2 | 2016-02-23 |
Mechanisms for eliminating a race condition between a hypervisor-performed emulation process requiring a translation operation and a concurrent translation table entry invalidation
Grant 9,251,088 - Frey , et al. February 2, 2 | 2016-02-02 |
Ensuring causality of transactional storage accesses interacting with non-transactional storage accesses
Grant 9,244,846 - Frey , et al. January 26, 2 | 2016-01-26 |
Managing Translations Across Multiple Contexts Using A Tlb With Entries Directed To Multiple Privilege Levels And To Multiple Types Of Address Spaces
App 20150301939 - BYBELL; Anthony J. ; et al. | 2015-10-22 |
Managing Translations Across Multiple Contexts Using A Tlb With Entries Directed To Multiple Privilege Levels And To Multiple Types Of Address Spaces
App 20150301951 - BYBELL; ANTHONY J. ; et al. | 2015-10-22 |
Managing Translation Of A Same Address Across Multiple Contexts Using A Same Entry In A Translation Lookaside Buffer
App 20150301950 - BYBELL; ANTHONY J. ; et al. | 2015-10-22 |
Managing Translation Of A Same Address Across Multiple Contexts Using A Same Entry In A Translation Lookaside Buffer
App 20150301953 - BYBELL; ANTHONY J. ; et al. | 2015-10-22 |
Conditional transaction abort and precise abort handling
Grant 9,081,607 - Blainey , et al. July 14, 2 | 2015-07-14 |
Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition
Grant 9,047,079 - Bruce , et al. June 2, 2 | 2015-06-02 |
Mechanisms For Eliminating A Race Condition Between A Hypervisor-performed Emulation Process Requiring A Translation Operation And A Concurrent Translation Table Entry Invalidation
App 20150120985 - Frey; Bradly G. ; et al. | 2015-04-30 |
Persistent prefetch data stream settings
Grant 8,856,453 - Dale , et al. October 7, 2 | 2014-10-07 |
Hardware-based Pre-page Walk Virtual Address Transformation
App 20140281353 - Bybell; Anthony J. ; et al. | 2014-09-18 |
Hardware-based Pre-page Walk Virtual Address Transformation
App 20140281209 - Bybell; Anthony J. ; et al. | 2014-09-18 |
Virtual Unified Instruction And Data Caches
App 20140281245 - Chen, JR.; Wen-Tzer Thomas ; et al. | 2014-09-18 |
Method And Apparatus For Conditional Transaction Abort And Precise Abort Handling
App 20140115590 - Blainey; Robert J ; et al. | 2014-04-24 |
Asymmetric Co-existent Address Translation Structure Formats
App 20140101359 - Bybell; Anthony J. ; et al. | 2014-04-10 |
Selectable Address Translation Mechanisms
App 20140101407 - Bybell; Anthony J. ; et al. | 2014-04-10 |
Asymmetric Co-existent Address Translation Structure Formats
App 20140101408 - Bybell; Anthony J. ; et al. | 2014-04-10 |
Selectable Address Translation Mechanisms
App 20140101404 - Bybell; Anthony J. ; et al. | 2014-04-10 |
Method And Apparatus For Recording And Profiling Transaction Failure Source Addresses In Hardware Transactional Memories
App 20140075441 - Blainey; Robert J. ; et al. | 2014-03-13 |
Interaction Of Transactional Storage Accesses With Other Atomic Semantics
App 20140047205 - FREY; BRADLY G. ; et al. | 2014-02-13 |
Transaction Check Instruction For Memory Transactions
App 20140047195 - FREY; Bradly G. ; et al. | 2014-02-13 |
Transaction Check Instruction For Memory Transactions
App 20140047196 - FREY; BRADLY G. ; et al. | 2014-02-13 |
Rewind Only Transactions In A Data Processing System Supporting Transactional Storage Accesses
App 20140040551 - BLAINEY; ROBERT J. ; et al. | 2014-02-06 |
Nested Rewind Only And Non Rewind Only Transactions In A Data Processing System Supporting Transactional Storage Accesses
App 20140040557 - FREY; BRADLY G. ; et al. | 2014-02-06 |
Ensuring Causality Of Transactional Storage Accesses Interacting With Non-transactional Storage Accesses
App 20140013060 - Frey; Bradly G. ; et al. | 2014-01-09 |
Ensuring Causality Of Transactional Storage Accesses Interacting With Non-transactional Storage Accesses
App 20140013055 - Frey; Bradly G. ; et al. | 2014-01-09 |
Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition
Grant 8,615,644 - Bruce , et al. December 24, 2 | 2013-12-24 |
Transactional memory preemption mechanism
Grant 8,544,022 - Arndt , et al. September 24, 2 | 2013-09-24 |
Persistent Prefetch Data Stream Settings
App 20130232320 - DALE; JASON N. ; et al. | 2013-09-05 |
Transactional memory preemption mechanism
Grant 8,424,015 - Arndt , et al. April 16, 2 | 2013-04-16 |
Using Hardware Transaction Primitives for Implementing Non-Transactional Escape Actions Inside Transactions
App 20130013899 - Barton; Christopher M. ; et al. | 2013-01-10 |
Transactional Memory Preemption Mechanism
App 20120246658 - Arndt; Richard L. ; et al. | 2012-09-27 |
Hardware Thread Disable With Status Indicating Safe Shared Resource Condition
App 20120185678 - Bruce; Becky ; et al. | 2012-07-19 |
Specifying an access hint for prefetching limited use data in a cache hierarchy
Grant 8,176,254 - Frey , et al. May 8, 2 | 2012-05-08 |
Transactional Memory Preemption Mechanism
App 20120084477 - Arndt; Richard L. ; et al. | 2012-04-05 |
Transactional Memory System Supporting Unbroken Suspended Execution
App 20110296148 - Cain, III; Harold W. ; et al. | 2011-12-01 |
Hardware Thread Disable With Status Indicating Safe Shared Resource Condition
App 20110208949 - Bruce; Becky ; et al. | 2011-08-25 |
Retaining an association between a virtual address based buffer and a user space application that owns the buffer
Grant 7,908,457 - Arndt , et al. March 15, 2 | 2011-03-15 |
Specifying An Access Hint For Prefetching Limited Use Data In A Cache Hierarchy
App 20100268885 - Frey; Bradly G. ; et al. | 2010-10-21 |
Retaining an Association Between a Virtual Address Based Buffer and a User Space Application that Owns the Buffer
App 20090276605 - Arndt; Richard L. ; et al. | 2009-11-05 |
Method and system for efficient bus allocation in a multimedia computer system
Grant 5,533,205 - Blackledge, Jr. , et al. July 2, 1 | 1996-07-02 |
Coordination of out-of-sequence fetching between multiple processors using re-execution of instructions
Grant 5,185,871 - Frey , et al. February 9, 1 | 1993-02-09 |
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