loadpatents
name:-0.0030779838562012
name:-0.022764921188354
name:-0.00053691864013672
Freidin; Philip M. Patent Filings

Freidin; Philip M.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Freidin; Philip M..The latest application filed is for "dispense verification meters".

Company Profile
0.19.2
  • Freidin; Philip M. - Sunnyvale CA US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Dispense verification meters
Grant 8,467,900 - Freidin June 18, 2
2013-06-18
Dispense Verification Meters
App 20120211518 - Freidin; Philip M.
2012-08-23
Dispense verification meters
Grant 8,185,237 - Freidin May 22, 2
2012-05-22
Dispense Verification Meters
App 20090171502 - Freidin; Philip M.
2009-07-02
High speed configurable transceiver architecture
Grant 7,187,709 - Menon , et al. March 6, 2
2007-03-06
Network physical layer with embedded multi-standard CRC generator
Grant 7,111,220 - Sasaki , et al. September 19, 2
2006-09-19
Configurable parallel and bit serial load apparatus
Grant 5,995,988 - Freidin , et al. November 30, 1
1999-11-30
Configurable parallel and bit serial load apparatus
Grant 5,961,576 - Freidin , et al. October 5, 1
1999-10-05
Configurable parallel and bit serial load apparatus
Grant 5,844,829 - Freidin , et al. December 1, 1
1998-12-01
Configurable parallel and bit serial load apparatus
Grant 5,742,531 - Freidin , et al. April 21, 1
1998-04-21
Virtual high density programmable integrated circuit having addressable shared memory cells
Grant 5,726,584 - Freidin March 10, 1
1998-03-10
Method for providing multiple function symbols
Grant 5,661,660 - Freidin August 26, 1
1997-08-26
Phase-locked delay loop for clock correction
Grant 5,646,564 - Erickson , et al. July 8, 1
1997-07-08
Synchronous dual port RAM
Grant 5,631,577 - Freidin , et al. May 20, 1
1997-05-20
Error detection structure and method for serial or parallel data stream using partial polynomial check
Grant 5,598,424 - Erickson , et al. January 28, 1
1997-01-28
Synchronous dual port ram
Grant 5,566,123 - Freidin , et al. October 15, 1
1996-10-15
Logic block with look-up table for configuration and memory
Grant 5,414,377 - Freidin May 9, 1
1995-05-09
Asynchronous or synchronous load multifunction flip-flop
Grant 5,410,194 - Freidin , et al. April 25, 1
1995-04-25
Error detection structure and method using partial polynomial check
Grant 5,321,704 - Erickson , et al. June 14, 1
1994-06-14
Streamlined instruction processor
Grant 4,926,323 - Baror , et al. May 15, 1
1990-05-15

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