Fraser; David B.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fraser; David B..The latest application filed is for "high dielectric constant metal oxide gate dielectrics".

Company Profile

0.31.6

Fraser; David B. - Danville CA
Fraser; David B. - Berkeley Heights NJ
Fraser; David B. - Maple Glen PA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
High dielectric constant metal oxide gate dielectrics Grant 6,998,357 - Bai , et al. February 14, 2	2006-02-14
In-plane on-chip decoupling capacitors and method for making same Grant 6,949,831 - Chiang , et al. September 27, 2	2005-09-27
High dielectric constant metal oxide gate dielectrics App 20050087820 - Bai, Gang ; et al.	2005-04-28
In-plane on-chip decoupling capacitors and method for making same App 20040245606 - Chiang, Chien ; et al.	2004-12-09
Method for capacitively coupling electronic devices Grant 6,790,704 - Doyle , et al. September 14, 2	2004-09-14
In-plane on-chip decoupling capacitors and method for making same Grant 6,777,320 - Chiang , et al. August 17, 2	2004-08-17
Method of fabricating image sensors using a thin film photodiode above active CMOS circuitry Grant 6,709,885 - Uppal , et al. March 23, 2	2004-03-23
High dielectric constant metal oxide gate dielectrics Grant 6,689,702 - Bai , et al. February 10, 2	2004-02-10
High dielectric constant metal oxide gate dielectrics App 20030075740 - Bai, Gang ; et al.	2003-04-24
Method of fabricating image sensors using a thin film photodiode above active CMOS circuitry App 20030057357 - Uppal, Jack S. ; et al.	2003-03-27
High dielectric constant metal oxide gate dielectrics Grant 6,528,856 - Bai , et al. March 4, 2	2003-03-04
Transistor With Reduced Series Resistance Junction Regions App 20010046744 - DOYLE, BRIAN S. ; et al.	2001-11-29
Method for Capacitively Coupling Electronic Devices App 20010039075 - Doyle, Brian ; et al.	2001-11-08
Fabricating low K dielectric interconnect systems by using dummy structures to enhance process Grant 6,309,956 - Chiang , et al. October 30, 2	2001-10-30
Apparatus for capacitively coupling electronic devices Grant 6,310,400 - Doyle , et al. October 30, 2	2001-10-30
Method for fabricating an interconnect structure with hard mask and low dielectric constant materials Grant 6,027,995 - Chiang , et al. February 22, 2	2000-02-22
Interconnect structure with hard mask and low dielectric constant materials Grant 5,886,410 - Chiang , et al. March 23, 1	1999-03-23
Unlanded via structure and method for making same Grant 5,880,030 - Fang , et al. March 9, 1	1999-03-09
Method of forming a polycide film Grant 5,861,340 - Bai , et al. January 19, 1	1999-01-19
Low temperature method of forming gate electrode and gate dielectric Grant 5,858,843 - Doyle , et al. January 12, 1	1999-01-12
Method for forming multileves interconnections for semiconductor fabrication Grant 5,817,572 - Chiang , et al. October 6, 1	1998-10-06
Polycide film Grant 5,818,092 - Bai , et al. October 6, 1	1998-10-06
Method of frabricating a MOS transistor having a composite gate electrode Grant 5,783,478 - Chau , et al. July 21, 1	1998-07-21
Method for forming interconnections for semiconductor fabrication and semiconductor device having such interconnections Grant 5,739,579 - Chiang , et al. April 14, 1	1998-04-14
Diffusion barrier for electrical interconnects in an integrated circuit Grant 5,714,418 - Bai , et al. February 3, 1	1998-02-03
MOS transistor having a composite gate electrode and method of fabrication Grant 5,625,217 - Chau , et al. April 29, 1	1997-04-29
Methods of forming an interconnect on a semiconductor substrate Grant 5,612,254 - Mu , et al. March 18, 1	1997-03-18
Method for the anisotropic etching of metal films in the fabrication of interconnects Grant 5,350,484 - Gardner , et al. September 27, 1	1994-09-27
Process for formation of a self aligned titanium nitride/cobalt silicide bilayer Grant 5,047,367 - Wei , et al. September 10, 1	1991-09-10
Process for selective contact hole filling including a silicide plug Grant 4,966,868 - Murali , et al. October 30, 1	1990-10-30
Alignment marks for electron beam lithography Grant 4,407,933 - Fraser , et al. October 4, 1	1983-10-04
Method of fabricating high-conductivity silicide-on-polysilicon structures for MOS devices Grant 4,362,597 - Fraser , et al. December 7, 1	1982-12-07
Silicon rich refractory silicides as gate metal Grant 4,337,476 - Fraser , et al. June 29, 1	1982-06-29
Fabrication of integrated circuits utilizing thick high-resolution patterns Grant 4,244,799 - Fraser , et al. January 13, 1	1981-01-13
Method for making patterned gold metallization Grant 4,072,768 - Fraser , et al. February 7, 1	1978-02-07
Image Motion Compensation Mechanism Grant 3,728,948 - Fraser April 24, 1	1973-04-24
Multiple Element Optical Memory Structures Using Fine Grain Ferroelectric Ceramics Grant 3,609,002 - Fraser , et al. September 28, 1	1971-09-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.