Frank; Martin Michael

Patent Applications and Registrations

Patent applications and USPTO patent grants for Frank; Martin Michael.The latest application filed is for "mitigating moisture driven degradation of silicon doped chalcogenides".

Company Profile

3.10.12

Frank; Martin Michael - Dobbs Ferry NY
Frank; Martin Michael - Summit NJ

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Mitigating Moisture Driven Degradation Of Silicon Doped Chalcogenides App 20220209113 - Cheng; Cheng-Wei ; et al.	2022-06-30
Magnesium Ion Based Synaptic Device App 20220045270 - Bishop; Douglas M. ; et al.	2022-02-10
Magnesium ion based synaptic device Grant 11,201,284 - Bishop , et al. December 14, 2	2021-12-14
Magnesium Ion Based Synaptic Device App 20210305504 - Bishop; Douglas M. ; et al.	2021-09-30
Sub-stoichiometric Metal-oxide Thin Films App 20210272796 - Rozen; John ; et al.	2021-09-02
Sub-stoichiometric metal-oxide thin films Grant 11,081,343 - Rozen , et al. August 3, 2	2021-08-03
Sub-stoichiometric Metal-oxide Thin Films App 20210020427 - Rozen; John ; et al.	2021-01-21
Ligand Selection For Ternary Oxide Thin Films App 20210020426 - Frank; Martin Michael ; et al.	2021-01-21
Ferroelectric Devices Free Of Extended Grain Boundaries App 20190245056 - Bruley; John ; et al.	2019-08-08
Engineering Multiple Threshold Voltages In An Integrated Circuit App 20150214323 - Dubourdieu; Catherine Anne ; et al.	2015-07-30
Engineering multiple threshold voltages in an integrated circuit Grant 9,041,082 - Dubourdieu , et al. May 26, 2	2015-05-26
High-K transistors with low threshold voltage Grant 8,598,027 - Frank December 3, 2	2013-12-03
Field-effect transistor device having a metal gate stack with an oxygen barrier layer Grant 8,415,677 - Adusumilli , et al. April 9, 2	2013-04-09
Engineering Multiple Threshold Voltages In An Integrated Circuit App 20120086059 - Dubourdieu; Catherine Anne ; et al.	2012-04-12
Process for fabricating a semiconductor device having an insulating layer formed over a semiconductor substrate Grant 7,223,677 - Frank , et al. May 29, 2	2007-05-29
Semiconductor device using an insulating layer having a seed layer Grant 6,825,538 - Frank , et al. November 30, 2	2004-11-30
Process for fabricating a semiconductor device having an insulating layer formed over a semiconductor substrate App 20040235313 - Frank, Martin Michael ; et al.	2004-11-25
Process for fabricating a semiconductor device having an insulating layer formed over a semiconductor substrate App 20040099889 - Frank, Martin Michael ; et al.	2004-05-27
Process for semiconductor device fabrication in which an insulating layer is formed over a semiconductor substrate App 20040094809 - Frank, Martin Michael ; et al.	2004-05-20

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.