Foo; Loke Yip

Patent Applications and Registrations

Patent applications and USPTO patent grants for Foo; Loke Yip.The latest application filed is for "chip assemblies".

Company Profile

5.5.9

Foo; Loke Yip - Bayan Baru MY
FOO; Loke Yip - Bayan Baru Pulau MY
Foo; Loke Yip - Ipoh MY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Power delivery for embedded interconnect bridge devices and methods Grant 11,393,758 - Cheah , et al. July 19, 2	2022-07-19
Chip Assemblies App 20220078914 - FOO; Loke Yip ; et al.	2022-03-10
Stacked Semiconductor Package With Flyover Bridge App 20220077070 - CHEE; Choong Kooi ; et al.	2022-03-10
Face-to-face Through-silicon Via Multi-chip Semiconductor Apparatus With Redistribution Layer Packaging And Methods Of Assembling Same App 20210391238 - Foo; Loke Yip ; et al.	2021-12-16
Face-to-face through-silicon via multi-chip semiconductor apparatus with redistribution layer packaging and methods of assembling same Grant 11,107,751 - Foo , et al. August 31, 2	2021-08-31
Embedded Dual-sided Interconnect Bridges For Integrated-circuit Packages App 20210098375 - Foo; Loke Yip ; et al.	2021-04-01
Power Delivery For Embedded Interconnect Bridge Devices And Methods App 20200083170 - Cheah; Bok Eng ; et al.	2020-03-12
Face-to-face Through-silicon Via Multi-chip Semiconductor Apparatus With Redistribution Layer Packaging And Methods Of Assemblin App 20190304876 - Foo; Loke Yip ; et al.	2019-10-03
Interconnection of an embedded die Grant 9,978,735 - Foo , et al. May 22, 2	2018-05-22
Interconnection Of An Embedded Die App 20180090474 - Foo; Loke Yip ; et al.	2018-03-29
Method to optimize general-purpose input/output interface pad assignments for integrated circuit Grant 9,842,181 - Oh , et al. December 12, 2	2017-12-12
Optimizing logic in non-reprogrammable logic devices Grant 7,081,772 - Foo July 25, 2	2006-07-25

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