Fontana; Fabiano

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fontana; Fabiano.The latest application filed is for "dual-port sram with bit line clamping".

Company Profile

0.25.3

Fontana; Fabiano - San Jose CA
Fontana; Fabiano - Santa Clara CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Dual-port SRAM with bit line clamping Grant 8,971,146 - Sharpe-Geisler , et al. March 3, 2	2015-03-03
Voltage discharge circuit having divided discharge current Grant 8,553,463 - Pollachek , et al. October 8, 2	2013-10-08
Dual-port Sram With Bit Line Clamping App 20130258761 - Sharpe-Geisler; Brad ; et al.	2013-10-03
Dual-port SRAM with bit line clamping Grant 8,451,679 - Sharpe-Geisler , et al. May 28, 2	2013-05-28
Bitline floating circuit for memory power reduction Grant 8,351,287 - Sood , et al. January 8, 2	2013-01-08
Flexible memory architectures for programmable logic devices Grant 7,957,208 - Tang , et al. June 7, 2	2011-06-07
Power management for integrated circuits such as programmable logic devices Grant 7,724,029 - Singh , et al. May 25, 2	2010-05-25
Programmable logic devices with custom identification systems and methods Grant 7,702,977 - Tang , et al. April 20, 2	2010-04-20
Power management systems and methods for programmable logic devices Grant 7,560,953 - Singh , et al. July 14, 2	2009-07-14
Programmable logic devices with user non-volatile memory Grant 7,554,358 - Fontana , et al. June 30, 2	2009-06-30
Programmable logic devices with custom identification systems and methods Grant 7,546,498 - Tang , et al. June 9, 2	2009-06-09
Flexible memory architectures for programmable logic devices Grant 7,495,970 - Tang , et al. February 24, 2	2009-02-24
Programmable logic devices with transparent field reconfiguration Grant 7,459,931 - Tang , et al. December 2, 2	2008-12-02
Programmable logic device providing a serial peripheral interface Grant 7,378,873 - Tang , et al. May 27, 2	2008-05-27
Zero-power programmable memory cell Grant RE40,311 - Mehta , et al. May 13, 2	2008-05-13
Flash memory erase verification systems and methods Grant 7,313,025 - Wong , et al. December 25, 2	2007-12-25
Flash memory erase verification systems and methods Grant 7,187,586 - Wong , et al. March 6, 2	2007-03-06
Variable source resistor for flash memory App 20070030736 - Fontana; Fabiano ; et al.	2007-02-08
Diode structure for word-line protection in a memory circuit App 20060145238 - Fontana; Fabiano ; et al.	2006-07-06
Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation Grant 6,838,904 - Agrawal , et al. January 4, 2	2005-01-04
Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use Grant 6,650,142 - Agrawal , et al. November 18, 2	2003-11-18
Zero-power programmable memory cell Grant 6,611,463 - Mehta , et al. August 26, 2	2003-08-26
Phase locked loop with a lock detector Grant 6,133,769 - Fontana , et al. October 17, 2	2000-10-17
CMOS logic gate clamping circuit Grant 5,442,304 - Wong , et al. August 15, 1	1995-08-15
High speed CMOS output buffer circuit minimizes propagation delay and crowbar current Grant 5,438,278 - Wong , et al. August 1, 1	1995-08-01
Input buffer circuit with improved speed performance Grant 5,402,081 - Wong , et al. March 28, 1	1995-03-28

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