Folberth; Harald D.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Folberth; Harald D..The latest application filed is for "layout of large block synthesis blocks in integrated circuits".

Company Profile

10.14.14

Folberth; Harald D. - Boeblingen DE

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Layout of large block synthesis blocks in integrated circuits Grant 10,534,884 - Barowski , et al. Ja	2020-01-14
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20190294739 - Barowski; Harry ; et al.	2019-09-26
Layout of large block synthesis blocks in integrated circuits Grant 10,417,366 - Barowski , et al. Sept	2019-09-17
Layout of large block synthesis blocks in integrated circuits Grant 10,366,191 - Barowski , et al. July 30, 2	2019-07-30
Layout of large block synthesis blocks in integrated circuits Grant 10,242,140 - Barowski , et al.	2019-03-26
Layout of large block synthesis blocks in integrated circuits Grant 10,235,487 - Barowski , et al.	2019-03-19
Placement clustering-based white space reservation Grant 10,223,489 - Barowski , et al.	2019-03-05
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20190065635 - Barowski; Harry ; et al.	2019-02-28
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20190065636 - Barowski; Harry ; et al.	2019-02-28
Area sharing between multiple large block synthesis (LBS) blocks Grant 10,169,519 - Barowski , et al. J	2019-01-01
Area Sharing Between Multiple Large Block Synthesis (lbs) Blocks App 20180189439 - Barowski; Harry ; et al.	2018-07-05
Placement Clustering-based White Space Reservation App 20180150584 - Barowski; Harry ; et al.	2018-05-31
Area sharing between multiple large block synthesis (LBS) blocks Grant 9,946,830 - Barowski , et al. April 17, 2	2018-04-17
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20180101626 - Barowski; Harry ; et al.	2018-04-12
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20180101625 - Barowski; Harry ; et al.	2018-04-12
Layout of large block synthesis blocks in integrated circuits Grant 9,928,329 - Barowski , et al. March 27, 2	2018-03-27
Layout of large block synthesis blocks in integrated circuits Grant 9,910,948 - Barowski , et al. March 6, 2	2018-03-06
Area Sharing Between Multiple Large Block Synthesis (lbs) Blocks App 20170351798 - Barowski; Harry ; et al.	2017-12-07
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20170212969 - Barowski; Harry ; et al.	2017-07-27
Layout Of Large Block Synthesis Blocks In Integrated Circuits App 20170212970 - Barowski; Harry ; et al.	2017-07-27
Circuit placement with electro-migration mitigation Grant 9,679,101 - Folberth , et al. June 13, 2	2017-06-13
Circuit placement with electro-migration mitigation Grant 9,536,037 - Folberth , et al. January 3, 2	2017-01-03
Circuit routing based on total negative slack Grant 9,483,601 - Folberth , et al. November 1, 2	2016-11-01
Circuit routing based on total negative slack Grant 9,471,741 - Folberth , et al. October 18, 2	2016-10-18
Circuit Routing Based On Total Negative Slack App 20160283637 - Folberth; Harald D. ; et al.	2016-09-29
Circuit Routing Based On Total Negative Slack App 20160283638 - Folberth; Harald D. ; et al.	2016-09-29
Circuit Placement With Electro-migration Mitigation App 20160267211 - Folberth; Harald D. ; et al.	2016-09-15
Circuit Placement With Electro-migration Mitigation App 20160267215 - Folberth; Harald D. ; et al.	2016-09-15

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