Fliesler; Michael David

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fliesler; Michael David.The latest application filed is for "combination field programmable gate array allowing dynamic reprogrammability and non-volatile programmability based upon transistor gate oxide breakdown".

Company Profile

0.5.4

Fliesler; Michael David - Santa Cruz CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric Grant 7,042,772 - Wang , et al. May 9, 2	2006-05-09
Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric Grant 7,031,209 - Wang , et al. April 18, 2	2006-04-18
Combination field programmable gate array allowing dynamic reprogrammability and non-votatile programmability based upon transistor gate oxide breakdown Grant 6,972,986 - Peng , et al. December 6, 2	2005-12-06
High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown Grant 6,940,751 - Peng , et al. September 6, 2	2005-09-06
Combination field programmable gate array allowing dynamic reprogrammability and non-volatile programmability based upon transistor gate oxide breakdown App 20050169039 - Peng, Jack Zezhong ; et al.	2005-08-04
Methods and circuits for programming of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric App 20040223370 - Wang, Jianguo ; et al.	2004-11-11
Methods and circuits for testing programmability of a semiconductor memory cell and memory array using a breakdown phenomenon in an ultra-thin dielectric App 20040208055 - Wang, Jianguo ; et al.	2004-10-21
High density semiconductor memory cell and memory array using a single transistor and having variable gate oxide breakdown App 20040156234 - Peng, Jack Zezhong ; et al.	2004-08-12
Method for improving electrostatic discharge (ESD) robustness Grant 6,238,975 - Fliesler , et al. May 29, 2	2001-05-29

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.