Fleischer; Bruce M.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Fleischer; Bruce M..The latest application filed is for "processor core, processor and method for executing a composite scalar-vector very lare instruction word (vliw) instruction".
Company Profile
3.65.62
- Fleischer; Bruce M. - Bedford Hills NY
- Fleischer; Bruce M. - Yorktown Heights NY
Patent Activity
| Patent | Date |
|---|---|
| Processor Core, Processor and Method for Executing a Composite Scalar-Vector Very Lare Instruction Word (VLIW) Instruction App 20200142704 - Fleischer; Bruce M. ; et al. | 2020-05-07 |
| Executing a composite VLIW instruction having a scalar atom that indicates an iteration of execution Grant 10,572,263 - Fleischer , et al. Feb | 2020-02-25 |
| Branch prediction in a computer processor Grant 10,275,256 - Fleischer , et al. | 2019-04-30 |
| Extendable conditional permute SIMD instructions Grant 10,162,634 - Eichenberger , et al. Dec | 2018-12-25 |
| Active memory device gather, scatter, and filter Grant 10,049,061 - Fleischer , et al. August 14, 2 | 2018-08-14 |
| Multi-petascale highly efficient parallel supercomputer Grant 9,971,713 - Asaad , et al. May 15, 2 | 2018-05-15 |
| High bandwidth low latency data exchange between processing elements Grant 9,928,190 - Fleischer , et al. March 27, 2 | 2018-03-27 |
| High bandwidth low latency data exchange between processing elements Grant 9,910,802 - Fleischer , et al. March 6, 2 | 2018-03-06 |
| On-chip traffic prioritization in memory Grant 9,841,926 - Fleischer , et al. December 12, 2 | 2017-12-12 |
| Test structure to measure delay variability mismatch of digital logic paths Grant 9,829,535 - Balakrishnan , et al. November 28, 2 | 2017-11-28 |
| Extendable Conditional Permute Simd Instructions App 20170337059 - EICHENBERGER; Alexander E. ; et al. | 2017-11-23 |
| Processor Core, Processor And Method For Executing A Composite Scalar-Vector Very Lare Instruction Word (VLIW) Instruction App 20170286108 - Fleischer; Bruce M. ; et al. | 2017-10-05 |
| Branch Prediction In A Computer Processor App 20170242701 - FLEISCHER; BRUCE M. ; et al. | 2017-08-24 |
| All-to-all permutation of vector elements based on a permutation pattern encoded in mantissa and exponent bits in a floating-point SIMD architecture Grant 9,652,231 - Eichenberger , et al. May 16, 2 | 2017-05-16 |
| Gather/scatter of multiple data elements with packed loading/storing into/from a register file entry Grant 9,632,777 - Fleischer , et al. April 25, 2 | 2017-04-25 |
| Gather/scatter of multiple data elements with packed loading/storing into /from a register file entry Grant 9,632,778 - Fleischer , et al. April 25, 2 | 2017-04-25 |
| Vector register file Grant 9,594,724 - Fleischer , et al. March 14, 2 | 2017-03-14 |
| Vector register file Grant 9,582,466 - Fleischer , et al. February 28, 2 | 2017-02-28 |
| Vector processing in an active memory device Grant 9,575,755 - Fleischer , et al. February 21, 2 | 2017-02-21 |
| SIMD compare instruction using permute logic for distributed register files Grant 9,575,753 - Eichenberger , et al. February 21, 2 | 2017-02-21 |
| Predication in a vector processor Grant 9,575,756 - Fleischer , et al. February 21, 2 | 2017-02-21 |
| Predication in a vector processor Grant 9,569,211 - Fleischer , et al. February 14, 2 | 2017-02-14 |
| Vector processing in an active memory device Grant 9,535,694 - Fleischer , et al. January 3, 2 | 2017-01-03 |
| Low Latency Data Exchange Between Processing Elements App 20160364364 - Fleischer; Bruce M. ; et al. | 2016-12-15 |
| Low Latency Data Exchange Between Processing Elements App 20160364352 - Fleischer; Bruce M. ; et al. | 2016-12-15 |
| On-chip Traffic Prioritization In Memory App 20160313947 - Fleischer; Bruce M. ; et al. | 2016-10-27 |
| On-chip traffic prioritization in memory Grant 9,405,711 - Fleischer , et al. August 2, 2 | 2016-08-02 |
| On-chip traffic prioritization in memory Grant 9,405,712 - Fleischer , et al. August 2, 2 | 2016-08-02 |
| Chaining between exposed vector pipelines Grant 9,400,656 - Fox , et al. July 26, 2 | 2016-07-26 |
| Test Structure To Measure Delay Variability Mismatch Of Digital Logic Paths App 20160209467 - Balakrishnan; Karthik ; et al. | 2016-07-21 |
| Power management for in-memory computer systems Grant 9,389,675 - Bose , et al. July 12, 2 | 2016-07-12 |
| Local bypass for in memory computing Grant 9,390,038 - Fleischer , et al. July 12, 2 | 2016-07-12 |
| Power management for a computer system Grant 9,329,664 - Bose , et al. May 3, 2 | 2016-05-03 |
| Local bypass in memory computing Grant 9,298,654 - Fleischer , et al. March 29, 2 | 2016-03-29 |
| Low latency data exchange Grant 9,274,971 - Fleischer , et al. March 1, 2 | 2016-03-01 |
| Low latency data exchange Grant 9,268,704 - Fleischer , et al. February 23, 2 | 2016-02-23 |
| Chaining between exposed vector pipelines Grant 9,250,916 - Fox , et al. February 2, 2 | 2016-02-02 |
| Memory page management Grant 9,251,048 - Fleischer , et al. February 2, 2 | 2016-02-02 |
| Multi-petascale Highly Efficient Parallel Supercomputer App 20160011996 - Asaad; Sameh ; et al. | 2016-01-14 |
| Power management for a computer system Grant 9,201,490 - Bose , et al. December 1, 2 | 2015-12-01 |
| Address generation in an active memory device Grant 9,110,778 - Fleischer , et al. August 18, 2 | 2015-08-18 |
| Sequential location accesses in an active memory device Grant 9,104,532 - Fleischer , et al. August 11, 2 | 2015-08-11 |
| Main processor support of tasks performed in memory Grant 9,104,464 - Fleischer , et al. August 11, 2 | 2015-08-11 |
| Main processor support of tasks performed in memory Grant 9,104,465 - Fleischer , et al. August 11, 2 | 2015-08-11 |
| Margin improvement for configurable local clock buffer Grant 9,088,279 - Fleischer , et al. July 21, 2 | 2015-07-21 |
| Multi-petascale highly efficient parallel supercomputer Grant 9,081,501 - Asaad , et al. July 14, 2 | 2015-07-14 |
| Power Management For In-memory Computer Systems App 20150177811 - Bose; Pradip ; et al. | 2015-06-25 |
| Active buffered memory Grant 9,003,160 - Fleischer , et al. April 7, 2 | 2015-04-07 |
| Margin Improvement For Configurable Local Clock Buffer App 20150084673 - Fleischer; Bruce M. ; et al. | 2015-03-26 |
| Exposed-pipeline processing element with rollback Grant 8,990,620 - Fleischer , et al. March 24, 2 | 2015-03-24 |
| Exposed-pipeline processing element with rollback Grant 8,972,782 - Fleischer , et al. March 3, 2 | 2015-03-03 |
| Power Management For A Computer System App 20140281629 - Bose; Pradip ; et al. | 2014-09-18 |
| Local Bypass For In Memory Computing App 20140281084 - Fleischer; Bruce M. ; et al. | 2014-09-18 |
| Local Bypass For In Memory Computing App 20140281100 - Fleischer; Bruce M. ; et al. | 2014-09-18 |
| Chaining Between Exposed Vector Pipelines App 20140281403 - Fox; Thomas W. ; et al. | 2014-09-18 |
| Power Management For A Computer System App 20140281605 - Bose; Pradip ; et al. | 2014-09-18 |
| Chaining Between Exposed Vector Pipelines App 20140281386 - Fox; Thomas W. ; et al. | 2014-09-18 |
| On-chip Traffic Prioritization In Memory App 20140195744 - Fleischer; Bruce M. ; et al. | 2014-07-10 |
| On-chip Traffic Prioritization In Memory App 20140195743 - Fleischer; Bruce M. ; et al. | 2014-07-10 |
| Sequential Location Accesses In An Active Memory Device App 20140173224 - Fleischer; Bruce M. ; et al. | 2014-06-19 |
| Low Latency Data Exchange App 20140149680 - Fleischer; Bruce M. ; et al. | 2014-05-29 |
| Low Latency Data Exchange App 20140149673 - Fleischer; Bruce M. ; et al. | 2014-05-29 |
| Exposed-pipeline Processing Element With Rollback App 20140136894 - Fleischer; Bruce M. ; et al. | 2014-05-15 |
| Active Memory Device Gather, Scatter, And Filter App 20140136811 - Fleischer; Bruce M. ; et al. | 2014-05-15 |
| Exposed-pipeline Processing Element With Rollback App 20140136895 - Fleischer; Bruce M. ; et al. | 2014-05-15 |
| Main Processor Support Of Tasks Performed In Memory App 20140130051 - Fleischer; Bruce M. ; et al. | 2014-05-08 |
| Address Generation In An Active Memory Device App 20140129799 - Fleischer; Bruce M. ; et al. | 2014-05-08 |
| Main Processor Support Of Tasks Performed In Memory App 20140130050 - Fleischer; Bruce M. ; et al. | 2014-05-08 |
| Memory Page Management App 20140115294 - Fleischer; Bruce M. ; et al. | 2014-04-24 |
| Automated critical area allocation in a physical synthesized hierarchical design Grant 8,656,332 - Fleischer , et al. February 18, 2 | 2014-02-18 |
| Vector Register File App 20140047214 - Fleischer; Bruce M. ; et al. | 2014-02-13 |
| Vector Register File App 20140047211 - Fleischer; Bruce M. ; et al. | 2014-02-13 |
| Vector Processing In An Active Memory Device App 20140040598 - Fleischer; Bruce M. ; et al. | 2014-02-06 |
| Packed Load/store With Gather/scatter App 20140040596 - Fleischer; Bruce M. ; et al. | 2014-02-06 |
| Predication In A Vector Processor App 20140040597 - Fleischer; Bruce M. ; et al. | 2014-02-06 |
| Packed Load/store With Gather/scatter App 20140040599 - Fleischer; Bruce M. ; et al. | 2014-02-06 |
| Vector Processing In An Active Memory Device App 20140040603 - Fleischer; Bruce M. ; et al. | 2014-02-06 |
| Active Buffered Memory App 20140040592 - Fleischer; Bruce M. ; et al. | 2014-02-06 |
| Predication In A Vector Processor App 20140040601 - Fleischer; Bruce M. ; et al. | 2014-02-06 |
| Register file soft error recovery Grant 8,560,924 - Fleischer , et al. October 15, 2 | 2013-10-15 |
| SIMD Compare Instruction Using Permute Logic for Distributed Register Files App 20130246737 - Eichenberger; Alexandre E. ; et al. | 2013-09-19 |
| Soft error detection for latches Grant 8,188,761 - Fleischer , et al. May 29, 2 | 2012-05-29 |
| Method and system for a wiring-efficient permute unit Grant 8,069,195 - Fleischer , et al. November 29, 2 | 2011-11-29 |
| Soft Error Detection For Latches App 20110221473 - Fleischer; Bruce M. ; et al. | 2011-09-15 |
| Multi-petascale Highly Efficient Parallel Supercomputer App 20110219208 - Asaad; Sameh ; et al. | 2011-09-08 |
| Soft error detection for latches Grant 7,977,965 - Fleischer , et al. July 12, 2 | 2011-07-12 |
| Aligning precision converted vector data using mask indicating offset relative to element boundary corresponding to precision type Grant 7,865,693 - Eichenberger , et al. January 4, 2 | 2011-01-04 |
| Automated Critical Area Allocation in a Physical Synthesized Hierarchical Design App 20100218155 - Fleischer; Bruce M. ; et al. | 2010-08-26 |
| Systems, methods and computer program products for providing a combined moduli-9 and 3 residue generator Grant 7,739,323 - Lipetz , et al. June 15, 2 | 2010-06-15 |
| System and method for a floating point unit with feedback prior to normalization and rounding Grant 7,730,117 - Fleischer , et al. June 1, 2 | 2010-06-01 |
| Scheme to optimize scan chain ordering in designs Grant 7,721,171 - Erle , et al. May 18, 2 | 2010-05-18 |
| Dynamically Aligning Enhanced Precision Vectors Based on Addresses Corresponding to Reduced Precision Vectors App 20100095086 - Eichenberger; Alexandre E. ; et al. | 2010-04-15 |
| Dynamic Data Driven Alignment and Data Formatting in a Floating-Point SIMD Architecture App 20100095087 - Eichenberger; Alexandre E. ; et al. | 2010-04-15 |
| System and method for performing decimal to binary conversion Grant 7,660,838 - Carlough , et al. February 9, 2 | 2010-02-09 |
| Method and System for a Wiring-Efficient Permute Unit App 20090177870 - Fleischer; Bruce M. ; et al. | 2009-07-09 |
| Scheme To Optimize Scan Chain Ordering In Designs App 20090049353 - Erle; Mark A. ; et al. | 2009-02-19 |
| Systems, Methods And Computer Program Products For Providing A Combined Moduli-9 And 3 Residue Generator App 20070294330 - Lipetz; Daniel ; et al. | 2007-12-20 |
| System and method for performing decimal to binary conversion App 20060179091 - Carlough; Steven R. ; et al. | 2006-08-10 |
| System and method for a fused multiply-add dataflow with early feedback prior to rounding App 20060179096 - Fleischer; Bruce M. ; et al. | 2006-08-10 |
| System and method for converting binary to decimal App 20060179090 - Carlough; Steven R. ; et al. | 2006-08-10 |
| System and method for a floating point unit with feedback prior to normalization and rounding App 20060179097 - Fleischer; Bruce M. ; et al. | 2006-08-10 |
| Processor design for extended-precision arithmetic Grant 6,842,765 - Enenkel , et al. January 11, 2 | 2005-01-11 |
| Processor design for extended-precision arithmetic App 20020107900 - Enenkel, Robert F. ; et al. | 2002-08-08 |
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