Flannagan; Stephen T.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Flannagan; Stephen T..The latest application filed is for "cascode sense amp and column select circuit and method of operation".
- Flannagan; Stephen T. - Austin TX
- Flannagan; Stephen T. - Beaverton OR
| Patent | Date |
|---|---|
| Cascode sense AMP and column select circuit and method of operation Grant 6,473,349 - Flannagan October 29, 2 | 2002-10-29 |
| Layout for noise reduction on a reference voltage Grant 5,670,815 - Childs , et al. September 23, 1 | 1997-09-23 |
| Delay locked loop for detecting the phase difference of two signals having different frequencies Grant 5,610,543 - Chang , et al. March 11, 1 | 1997-03-11 |
| Write control for a memory using a delay locked loop Grant 5,440,514 - Flannagan , et al. August 8, 1 | 1995-08-08 |
| Delay locked loop for detecting the phase difference of two signals having different frequencies Grant 5,440,515 - Chang , et al. August 8, 1 | 1995-08-08 |
| Latching ECL to CMOS input buffer circuit Grant 5,426,381 - Flannagan , et al. June 20, 1 | 1995-06-20 |
| Synchronous memory having parallel output data paths Grant 5,402,389 - Flannagan , et al. March 28, 1 | 1995-03-28 |
| Pipelined memory having synchronous and asynchronous operating modes Grant 5,384,737 - Childs , et al. January 24, 1 | 1995-01-24 |
| BICMOS sense amplifier with reverse bias protection Grant 5,287,314 - Flannagan , et al. February 15, 1 | 1994-02-15 |
| BICMOS combined bit line load and write gate for a memory Grant 5,173,877 - Flannagan , et al. December 22, 1 | 1992-12-22 |
| Logic level shifting circuit with minimal delay Grant 5,059,829 - Flannagan , et al. October 22, 1 | 1991-10-22 |
| Non-address transition detection memory with improved access time Grant 4,964,083 - Nogle , et al. October 16, 1 | 1990-10-16 |
| Memory using distributed data line loading Grant 4,928,268 - Nogle , et al. May 22, 1 | 1990-05-22 |
| Redundancy for a block-architecture memory Grant 4,807,191 - Flannagan February 21, 1 | 1989-02-21 |
| Write-drive data controller Grant 4,763,303 - Flannagan August 9, 1 | 1988-08-09 |
| High performance output driver Grant 4,716,550 - Flannagan , et al. December 29, 1 | 1987-12-29 |
| Identity circuit for an integrated circuit using a fuse and transistor enabled by a power-on reset signal Grant 4,716,302 - Flannagan , et al. December 29, 1 | 1987-12-29 |
| Memory architecture with sub-arrays Grant 4,698,788 - Flannagan , et al. October 6, 1 | 1987-10-06 |
| Asynchronous row and column control Grant 4,661,931 - Flannagan , et al. April 28, 1 | 1987-04-28 |
| Bit line precharge on a column address change Grant 4,658,381 - Reed , et al. April 14, 1 | 1987-04-14 |
| Tri-state differential amplifier Grant 4,644,196 - Flannagan February 17, 1 | 1987-02-17 |
| Reduced power sense amplifier Grant 4,644,197 - Flannagan February 17, 1 | 1987-02-17 |
| Summation of address transition signals Grant 4,636,991 - Flannagan , et al. January 13, 1 | 1987-01-13 |
| Chip select speed-up circuit for a memory Grant 4,630,239 - Reed , et al. December 16, 1 | 1986-12-16 |
| Multiple bit dynamic random-access memory Grant 4,547,867 - Reese , et al. October 15, 1 | 1985-10-15 |
| Testing method and apparatus for dram Grant 4,468,759 - Kung , et al. August 28, 1 | 1984-08-28 |
| Multiple bit output dynamic random-access memory Grant 4,453,237 - Reese , et al. June 5, 1 | 1984-06-05 |
| Byte-wide dynamic RAM with multiplexed internal buses Grant 4,449,207 - Kung , et al. May 15, 1 | 1984-05-15 |
| Multiple bit output dynamic random-access memory Grant 4,406,013 - Reese , et al. September 20, 1 | 1983-09-20 |
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