loadpatents
name:-0.03590989112854
name:-0.031754970550537
name:-0.0064249038696289
Flachs; Brian Patent Filings

Flachs; Brian

Patent Applications and Registrations

Patent applications and USPTO patent grants for Flachs; Brian.The latest application filed is for "arranging binary code based on call graph partitioning".

Company Profile
6.41.32
  • Flachs; Brian - Georgetown TX
  • Flachs; Brian - Austin TX US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Arranging binary code based on call graph partitioning
Grant 10,324,694 - Chen , et al.
2019-06-18
Arranging binary code based on call graph partitioning
Grant 10,169,013 - Chen , et al. J
2019-01-01
Arranging Binary Code Based on Call Graph Partitioning
App 20180136918 - Chen; Tong ;   et al.
2018-05-17
Arranging binary code based on call graph partitioning
Grant 9,916,144 - Chen , et al. March 13, 2
2018-03-13
Arranging Binary Code Based on Call Graph Partitioning
App 20170161040 - Chen; Tong ;   et al.
2017-06-08
Selection of post-request action based on combined response and input from the request source
Grant 9,606,922 - Blaner , et al. March 28, 2
2017-03-28
Arranging binary code based on call graph partitioning
Grant 9,600,253 - Chen , et al. March 21, 2
2017-03-21
Selection of post-request action based on combined response and input from the request source
Grant 9,547,597 - Blaner , et al. January 17, 2
2017-01-17
Arranging Binary Code Based on Call Graph Partitioning
App 20170010873 - Chen; Tong ;   et al.
2017-01-12
Arranging binary code based on call graph partitioning
Grant 9,459,851 - Chen , et al. October 4, 2
2016-10-04
Performing secure address relocation within a multi-processor system sharing a same physical memory channel to external memory
Grant 9,424,173 - Dinkjian , et al. August 23, 2
2016-08-23
Performing Secure Address Relocation Within A Multi-processor System Sharing A Same Physical Memory Channel To External Memory
App 20160117240 - DINKJIAN; ROBERT M. ;   et al.
2016-04-28
Efficient multi-level software cache using SIMD vector permute functionality
Grant 8,862,827 - Flachs , et al. October 14, 2
2014-10-14
Selection Of Post-request Action Based On Combined Response And Input From The Request Source
App 20140250275 - BLANER; BARTHOLOMEW ;   et al.
2014-09-04
Selection Of Post-request Action Based On Combined Response And Input From The Request Source
App 20140250276 - BLANER; BARTHOLOMEW ;   et al.
2014-09-04
Dynamically rewriting branch instructions in response to cache line eviction
Grant 8,782,381 - Chen , et al. July 15, 2
2014-07-15
Management of conditional branches within a data parallel system
Grant 8,726,252 - Eichenberger , et al. May 13, 2
2014-05-13
Rewriting branch instructions using branch stubs
Grant 8,713,548 - Chen , et al. April 29, 2
2014-04-29
Ceasing parallel processing of first set of loops upon selectable number of monitored terminations and processing second set
Grant 8,683,185 - Flachs , et al. March 25, 2
2014-03-25
Method and apparatus for cooperative software multitasking in a processor system with a partitioned register file
Grant 8,677,101 - Flachs , et al. March 18, 2
2014-03-18
Dynamically rewriting branch instructions to directly target an instruction cache location
Grant 8,631,225 - Chen , et al. January 14, 2
2014-01-14
Dynamically rewriting branch instructions to directly target an instruction cache location
Grant 8,627,051 - Chen , et al. January 7, 2
2014-01-07
Rewriting branch instructions using branch stubs
Grant 8,522,225 - Chen , et al. August 27, 2
2013-08-27
Arithmetic decoding acceleration
Grant 8,520,740 - Flachs , et al. August 27, 2
2013-08-27
SPE software instruction cache
Grant 8,516,230 - Chen , et al. August 20, 2
2013-08-20
Optimization of software instruction cache by line re-ordering
Grant 8,359,435 - Erez , et al. January 22, 2
2013-01-22
Rewriting Branch Instructions Using Branch Stubs
App 20120204016 - Chen; Tong ;   et al.
2012-08-09
Arranging Binary Code Based on Call Graph Partitioning
App 20120198429 - Chen; Tong ;   et al.
2012-08-02
Binary Rewriting in Software Instruction Cache
App 20120198169 - Chen; Tong ;   et al.
2012-08-02
Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction
App 20120198170 - Chen; Tong ;   et al.
2012-08-02
Management Of Conditional Branches Within A Data Parallel System
App 20120198425 - Eichenberger; Alexandre E. ;   et al.
2012-08-02
Secure Page Tables in Multiprocessor Environments
App 20120110348 - Hofstee; H. Peter ;   et al.
2012-05-03
Arithmetic Decoding Acceleration
App 20120057637 - Flachs; Brian ;   et al.
2012-03-08
Parallel Loop Management
App 20120023316 - Flachs; Brian ;   et al.
2012-01-26
Arranging Binary Code Based on Call Graph Partitioning
App 20110321021 - Chen; Tong ;   et al.
2011-12-29
Rewriting Branch Instructions Using Branch Stubs
App 20110321002 - Chen; Tong ;   et al.
2011-12-29
Dynamically Rewriting Branch Instructions in Response to Cache Line Eviction
App 20110320786 - Chen; Tong ;   et al.
2011-12-29
Binary Rewriting in Software Instruction Cache
App 20110320785 - Chen; Tong ;   et al.
2011-12-29
SPE Software Instruction Cache
App 20110161641 - CHEN; TONG ;   et al.
2011-06-30
Efficient Multi-Level Software Cache Using SIMD Vector Permute Functionality
App 20110161548 - Flachs; Brian ;   et al.
2011-06-30
On-line Optimization Of Software Instruction Cache
App 20110145503 - Erez; Revital ;   et al.
2011-06-16
System for limiting the size of a local storage of a processor
Grant 7,730,279 - Burns , et al. June 1, 2
2010-06-01
Middlesoft commander
Grant 7,689,865 - Baier , et al. March 30, 2
2010-03-30
Modifying a test pattern to control power supply noise
Grant 7,610,531 - Dhong , et al. October 27, 2
2009-10-27
System for Limiting the Size of a Local Storage of a Processor
App 20090204781 - Burns; Adam P. ;   et al.
2009-08-13
Method for limiting the size of a local storage of a processor
Grant 7,533,238 - Burns , et al. May 12, 2
2009-05-12
Design Structure For A Processor System With Background Error Handling Feature
App 20090070654 - Flachs; Brian ;   et al.
2009-03-12
Method and apparatus for testing to determine minimum operating voltages in electronic devices
Grant 7,486,096 - Dhong , et al. February 3, 2
2009-02-03
Method and Apparatus for Cooperative Software Multitasking In A Processor System with a Partitioned Register File
App 20080307201 - Flachs; Brian ;   et al.
2008-12-11
System and method for sorting processors based on thermal design point
Grant 7,447,602 - Bradley , et al. November 4, 2
2008-11-04
System and Method for Determining a Guard Band for an Operating Voltage of an Integrated Circuit Device
App 20080189090 - Aikawa; Makoto ;   et al.
2008-08-07
Stimulating And Receiving Test/debug Data From A System Under Test Via A Drone Card Pci Bus
App 20080126632 - Baier; Heinz ;   et al.
2008-05-29
Middlesoft Commander
App 20080126895 - Baier; Heinz ;   et al.
2008-05-29
Method and Apparatus for Testing to Determine Minimum Operating Voltages in Electronic Devices
App 20080100328 - Dhong; Sang H. ;   et al.
2008-05-01
Optimizing a Set of LBIST Patterns to Enhance Delay Fault Coverage
App 20080092006 - Dakwala; Nikhil ;   et al.
2008-04-17
System and Method for Modifying a Test Pattern to Control Power Supply Noise
App 20080082887 - Dhong; Sang H. ;   et al.
2008-04-03
Processor system and methodology with background error handling feature
App 20070186135 - Flachs; Brian ;   et al.
2007-08-09
Impedane measurement of chip, package, and board power supply system using pseudo impulse response
Grant 7,203,608 - Aikawa , et al. April 10, 2
2007-04-10
System and method for limiting the size of a local storage of a processor
App 20070043926 - Burns; Adam P. ;   et al.
2007-02-22

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.

© 2024 USPTO.report | Privacy Policy | Resources | RSS Feed of Trademarks | Trademark Filings Twitter Feed