loadpatents
name:-0.018683910369873
name:-0.022313117980957
name:-0.00048589706420898
Fischer; Jeffrey Herbert Patent Filings

Fischer; Jeffrey Herbert

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fischer; Jeffrey Herbert.The latest application filed is for "automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems".

Company Profile
0.22.19
  • Fischer; Jeffrey Herbert - Raleigh NC US
  • Fischer; Jeffrey Herbert - Cary NC US
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
Method and apparatus to enable a selective push process during manufacturing to improve performance of a selected circuit of an integrated circuit
Grant 9,495,503 - Fischer , et al. November 15, 2
2016-11-15
Automatic calibration circuits for operational calibration of critical-path time delays in adaptive clock distribution systems, and related methods and systems
Grant 9,413,344 - Bowman , et al. August 9, 2
2016-08-09
Automatic Calibration Circuits For Operational Calibration Of Critical-path Time Delays In Adaptive Clock Distribution Systems, And Related Methods And Systems
App 20160072491 - Bowman; Keith Alan ;   et al.
2016-03-10
Mimicking multi-voltage domain wordline decoding logic for a memory array
Grant 9,196,330 - Ge , et al. November 24, 2
2015-11-24
Bi-modal power delivery scheme for an integrated circuit comprising multiple functional blocks on a single die to achieve desired average throughput for the integrated circuit
Grant 9,134,777 - Kolla , et al. September 15, 2
2015-09-15
Pulse clock generation logic with built-in level shifter and programmable rising edge and pulse width
Grant 8,638,153 - Ge , et al. January 28, 2
2014-01-28
Bi-Modal Power Delivery Scheme for Integrated Circuits that Enables Fine Grain Power Management for Multiple Functional Blocks on a Single Die
App 20130332748 - Kolla; Yeshwant Nagaraj ;   et al.
2013-12-12
Pulse Clock Generation Logic with Built-in Level Shifter and Programmable Rising Edge and Pulse Width
App 20130257498 - Ge; Shaoping ;   et al.
2013-10-03
Mimicking Multi-Voltage Domain Wordline Decoding Logic for a Memory Array
App 20130182514 - Ge; Shaoping ;   et al.
2013-07-18
Method and Apparatus to Enable a Selective Push Process During Manufacturing to Improve Performance of a Selected Circuit of an Integrated Circuit
App 20120256682 - Fischer; Jeffrey Herbert ;   et al.
2012-10-11
Method and apparatus for reducing power consumption in a content addressable memory
Grant 8,154,900 - Chai , et al. April 10, 2
2012-04-10
High speed CAM lookup using stored encoded key
Grant 7,761,774 - Fischer , et al. July 20, 2
2010-07-20
Method And Apparatus For Reducing Power Consumption In A Content Addressable Memory
App 20100023684 - CHAI; CHIAMING ;   et al.
2010-01-28
Method and apparatus for reducing power consumption in a content addressable memory
Grant 7,616,468 - Chai , et al. November 10, 2
2009-11-10
Method and apparatus for aborting content addressable memory search operations
Grant 7,586,772 - Chai , et al. September 8, 2
2009-09-08
Logic state catching circuits
Grant 7,564,266 - Ge , et al. July 21, 2
2009-07-21
Logic State Catching Circuits
App 20080315919 - Ge; Shaoping ;   et al.
2008-12-25
Method and Apparatus for Aborting Content Addressable Memory Search Operations
App 20080031040 - Chai; Chiaming ;   et al.
2008-02-07
Method and Apparatus for Reducing Power Consumption in a Content Addressable Memory
App 20080031033 - Chai; Chiaming ;   et al.
2008-02-07
Multimode, uniform-latency clock generation circuit
Grant 7,301,384 - Hamdan , et al. November 27, 2
2007-11-27
Method and apparatus for reducing clock enable setup time in a multi-enabled clock gating circuit
Grant 7,279,935 - Hamdan , et al. October 9, 2
2007-10-09
Multimode, uniform-latency clock generation circuit
App 20070229134 - Hamdan; Fadi Adel ;   et al.
2007-10-04
Method and apparatus for reducing clock enable setup time in a multi-enabled clock gating circuit
App 20070210833 - Hamdan; Fadi Adel ;   et al.
2007-09-13
Methods and apparatus for reading a full-swing memory array
Grant 7,242,624 - Kolla , et al. July 10, 2
2007-07-10
Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground
Grant 7,242,600 - Phan , et al. July 10, 2
2007-07-10
High speed CAM lookup using stored encoded key
App 20070113158 - Fischer; Jeffrey Herbert ;   et al.
2007-05-17
Circuit and method for subdividing a CAMRAM bank by controlling a virtual ground
App 20070097722 - Phan; Michael ThaiThanh ;   et al.
2007-05-03
Methods and apparatus for reading a full-swing memory array
App 20060280003 - Kolla; Yeshwant N. ;   et al.
2006-12-14
Apparatus for detecting multiple hits in a CAMRAM memory array
Grant 6,816,396 - Chai , et al. November 9, 2
2004-11-09
Apparatus For Detecting Multiple Hits In A Camram Memory Array
App 20040196700 - Chai, Chiaming ;   et al.
2004-10-07
Strobe circuit keeper arrangement providing reduced power consumption
Grant 6,535,041 - Bucki , et al. March 18, 2
2003-03-18
Method and structure for a CAMRAM cache memory
App 20020159283 - Chai, Chiaming ;   et al.
2002-10-31
Segmented match line arrangement for content addressable memory
Grant 6,452,822 - Chai , et al. September 17, 2
2002-09-17
Redundant scheme for CAMRAM memory array
Grant 6,385,071 - Chai , et al. May 7, 2
2002-05-07

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