| Patent | Date |
|---|
Snoop blocking for cache coherency
Grant 6,668,309 - Bachand , et al. December 23, 2 | 2003-12-23 |
Snoop blocking for cache coherency
App 20030115424 - Bachand, Derek T. ; et al. | 2003-06-19 |
Snoop blocking for cache coherency
Grant 6,578,116 - Bachand , et al. June 10, 2 | 2003-06-10 |
Snoop blocking for cache coherency
App 20020199068 - Bachand, Derek T. ; et al. | 2002-12-26 |
Snoop blocking for cache coherency
Grant 6,460,119 - Bachand , et al. October 1, 2 | 2002-10-01 |
Core clock correction in a 2/n mode clocking scheme
Grant 6,268,749 - Fisch , et al. July 31, 2 | 2001-07-31 |
Read line buffer and signaling protocol for processor
Grant 6,209,068 - Hill , et al. March 27, 2 | 2001-03-27 |
Core clock correction in a 2/N mode clocking scheme
Grant 6,208,180 - Fisch , et al. March 27, 2 | 2001-03-27 |
Apparatus for generating bus clock signals with a 1/N characteristic in a 2/N mode clocking scheme
Grant 6,114,887 - Pathikonda , et al. September 5, 2 | 2000-09-05 |
Transaction stall technique to prevent livelock in multiple-processor systems
Grant 6,078,981 - Hill , et al. June 20, 2 | 2000-06-20 |
Apparatus and method for caching lock conditions in a multi-processor system
Grant 6,006,299 - Wang , et al. December 21, 1 | 1999-12-21 |
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
Grant 5,909,699 - Sarangdhar , et al. June 1, 1 | 1999-06-01 |
Computer system providing a universal architecture adaptive to a variety of processor types and bus protocols
Grant 5,896,513 - Fisch , et al. April 20, 1 | 1999-04-20 |
Signaling protocol conversion between a processor and a high-performance system bus
Grant 5,845,107 - Fisch , et al. December 1, 1 | 1998-12-01 |
Method and apparatus for preventing logic glitches in a 2/n clocking scheme
Grant 5,826,067 - Fisch , et al. October 20, 1 | 1998-10-20 |
Method and apparatus for self-snooping a bus during a boundary transaction
Grant 5,797,026 - Rhodehamel , et al. August 18, 1 | 1998-08-18 |
Method and apparatus for dynamically controlling bus access from a bus agent based on bus pipeline depth
Grant 5,784,579 - Pawlowski , et al. July 21, 1 | 1998-07-21 |
Method and apparatus for accessing split lock variables in a computer system
Grant 5,778,441 - Rhodehamel , et al. July 7, 1 | 1998-07-07 |
Method and apparatus for determining the timing of snoop windows in a pipelined bus
Grant 5,774,700 - Fisch , et al. June 30, 1 | 1998-06-30 |
Processor subsystem for use with a universal computer architecture
Grant 5,764,934 - Fisch , et al. June 9, 1 | 1998-06-09 |
Computer system with distributed bus arbitration scheme for symmetric and priority agents
Grant 5,581,782 - Sarangdhar , et al. December 3, 1 | 1996-12-03 |
Method and apparatus for supporting read, write, and invalidation operations to memory which maintain cache consistency
Grant 5,572,702 - Sarangdhar , et al. November 5, 1 | 1996-11-05 |
Initialization mechanism for symmetric arbitration agents
Grant 5,515,516 - Fisch , et al. May 7, 1 | 1996-05-07 |
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