Finchelstein; Daniel Frederic

Patent Applications and Registrations

Patent applications and USPTO patent grants for Finchelstein; Daniel Frederic.The latest application filed is for "convolutional neural network on programmable two dimensional image processor".

Company Profile

30.34.39

Finchelstein; Daniel Frederic - Redwood City CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register Grant 11,196,953 - Meixner , et al. December 7, 2	2021-12-07
Line buffer unit for image processor Grant 11,190,718 - Desai , et al. November 30, 2	2021-11-30
Two dimensional shift array for image processor Grant 11,153,464 - Shacham , et al. October 19, 2	2021-10-19
Energy efficient processor core architecture for image processor Grant 11,138,013 - Meixner , et al. October 5, 2	2021-10-05
Sheet generator for image processor Grant 11,140,293 - Meixner , et al. October 5, 2	2021-10-05
Statistics operations on two dimensional image processor Grant 10,915,773 - Chang , et al. February 9, 2	2021-02-09
Energy Efficient Processor Core Architecture for Image Processor App 20210004232 - Meixner; Albert ; et al.	2021-01-07
Convolutional Neural Network On Programmable Two Dimensional Image Processor App 20210004633 - Shacham; Ofer ; et al.	2021-01-07
Convolutional neural network on programmable two dimensional image processor Grant 10,789,505 - Shacham , et al. September 29, 2	2020-09-29
Virtual linebuffers for image signal processors Grant 10,791,284 - Zhu , et al. September 29, 2	2020-09-29
Line Buffer Unit for Image Processor App 20200275040 - Desai; Neeti ; et al.	2020-08-27
Energy efficient processor core architecture for image processor Grant 10,754,654 - Meixner , et al. A	2020-08-25
Architecture for high performance, power efficient, programmable image processing Grant 10,719,905 - Zhu , et al.	2020-07-21
Sheet Generator For Image Processor App 20200186667 - Meixner; Albert ; et al.	2020-06-11
Block Operations For An Image Processor Having A Two-dimensional Execution Lane Array And A Two-dimensional Shift Register App 20200154072 - Meixner; Albert ; et al.	2020-05-14
Line buffer unit for image processor Grant 10,638,073 - Desai , et al.	2020-04-28
Virtual Linebuffers For Image Signal Processors App 20200120287 - Zhu; Qiuling ; et al.	2020-04-16
Sheet generator for image processor Grant 10,560,598 - Meixner , et al. Feb	2020-02-11
Convolutional neural network on programmable two dimensional image processor Grant 10,546,211 - Shacham , et al. Ja	2020-01-28
Compiler Techniques For Mapping Program Code To A High Performance, Power Efficient, Programmable Image Processing Hardware Plat App 20200020069 - Meixner; Albert ; et al.	2020-01-16
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register Grant 10,531,030 - Meixner , et al. J	2020-01-07
Virtual linebuffers for image signal processors Grant 10,516,833 - Zhu , et al. Dec	2019-12-24
Architecture For High Performance, Power Efficient, Programmable Image Processing App 20190378239 - Zhu; Qiuling ; et al.	2019-12-12
Two Dimensional Shift Array for Image Processor App 20190364174 - Shacham; Ofer ; et al.	2019-11-28
Line Buffer Unit for Image Processor App 20190327433 - Desai; Neeti ; et al.	2019-10-24
Block Operations For An Image Processor Having A Two-dimensional Execution Lane Array And A Two-dimensional Shift Register App 20190327437 - Meixner; Albert ; et al.	2019-10-24
Architecture for high performance, power efficient, programmable image processing Grant 10,417,732 - Zhu , et al. Sept	2019-09-17
Two dimensional shift array for image processor Grant 10,397,450 - Shacham , et al. A	2019-08-27
Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform Grant 10,387,989 - Meixner , et al. A	2019-08-20
Compiler techniques for mapping program code to a high performance, power efficient, programmable image processing hardware platform Grant 10,387,988 - Meixner , et al. A	2019-08-20
Virtual Linebuffers For Image Signal Processors App 20190238758 - Zhu; Qiuling ; et al.	2019-08-01
Energy Efficient Processor Core Architecture for Image Processor App 20190220282 - Meixner; Albert ; et al.	2019-07-18
Sheet Generator For Image Processor App 20190208075 - Meixner; Albert ; et al.	2019-07-04
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register Grant 10,334,194 - Meixner , et al.	2019-06-25
Line buffer unit for image processor Grant 10,321,077 - Desai , et al.	2019-06-11
Sheet generator for image processor Grant 10,291,813 - Meixner , et al.	2019-05-14
Sheet generator for image processor Grant 10,284,744 - Meixner , et al.	2019-05-07
Virtual linebuffers for image signal processors Grant 10,277,833 - Zhu , et al.	2019-04-30
Energy efficient processor core architecture for image processor Grant 10,275,253 - Meixner , et al.	2019-04-30
Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure Grant 10,216,487 - Meixner , et al. Feb	2019-02-26
Virtual image processor instruction set architecture (ISA) and memory model and exemplary target hardware having a two-dimensional shift array structure Grant 10,095,479 - Meixner , et al. October 9, 2	2018-10-09
Block Operations For An Image Processor Having A Two-dimensional Execution Lane Array And A Two-dimensional Shift Register App 20180234653 - Meixner; Albert ; et al.	2018-08-16
Block operations for an image processor having a two-dimensional execution lane array and a two-dimensional shift register Grant 9,986,187 - Meixner , et al. May 29, 2	2018-05-29
Core processes for block operations on an image processor having a two-dimensional execution lane array and a two-dimensional shift register Grant 9,978,116 - Meixner , et al. May 22, 2	2018-05-22
Architecture for high performance, power efficient, programmable image processing Grant 9,965,824 - Zhu , et al. May 8, 2	2018-05-08
Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and a Two-Dimensional Shift Register App 20180005347 - Meixner; Albert ; et al.	2018-01-04
Convolutional Neural Network On Programmable Two Dimensional Image Processor App 20180005074 - SHACHAM; Ofer ; et al.	2018-01-04
Block Operations For An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register App 20180007302 - MEIXNER; Albert ; et al.	2018-01-04
Statistics Operations On Two Dimensional Image Processor App 20180005059 - CHANG; Edward ; et al.	2018-01-04
Convolutional Neural Network On Programmable Two Dimensional Image Processor App 20180005075 - Shacham; Ofer ; et al.	2018-01-04
Core Processes For Block Operations On An Image Processor Having A Two-Dimensional Execution Lane Array and A Two-Dimensional Shift Register App 20180005346 - MEIXNER; Albert ; et al.	2018-01-04
Block Operations For An Image Processor Having A Two-dimensional Execution Lane Array And A Two-dimensional Shift Register App 20180007303 - Meixner; Albert ; et al.	2018-01-04
Statistics Operations On Two Dimensional Image Processor App 20180005061 - Chang; Edward ; et al.	2018-01-04
Two Dimensional Shift Array for Image Processor App 20170310855 - Shacham; Ofer ; et al.	2017-10-26
Compiler Techniques For Mapping Program Code To A High Performance, Power Efficient, Programmable Image Processing Hardware Platform App 20170287103 - Meixner; Albert ; et al.	2017-10-05
Energy efficient processor core architecture for image processor Grant 9,772,852 - Meixner , et al. September 26, 2	2017-09-26
Two dimensional shift array for image processor Grant 9,769,356 - Shacham , et al. September 19, 2	2017-09-19
Architecture For High Performance, Power Efficient, Programmable Image Processing App 20170256021 - Zhu; Qiuling ; et al.	2017-09-07
Line Buffer Unit For Image Processor App 20170257585 - Desai; Neeti ; et al.	2017-09-07
Sheet Generator For Image Processor App 20170257515 - Meixner; Albert ; et al.	2017-09-07
Line buffer unit for image processor Grant 9,756,268 - Desai , et al. September 5, 2	2017-09-05
Compiler Techniques for Mapping Program Code to a High Performance, Power Efficient, Programmable Image Processing Hardware Platform App 20170249716 - MEIXNER; Albert ; et al.	2017-08-31
Energy Efficient Processor Core Architecture for Image Processor App 20170249153 - Meixner; Albert ; et al.	2017-08-31
Virtual linebuffers for image signal processors Grant 9,749,548 - Zhu , et al. August 29, 2	2017-08-29
Virtual Image Processor Instruction Set Architecture (ISA) And Memory Model And Exemplary Target Hardware Having A Two-Dimensional Shift Array Structure App 20170242943 - Meixner; Albert ; et al.	2017-08-24
Virtual Linebuffers For Image Signal Processors App 20170206627 - Zhu; Qiuling ; et al.	2017-07-20
Virtual Image Processor Instruction Set Architecture (ISA) And Memory Model And Exemplary Target Hardware Having A Two-Dimensional Shift Array Structure App 20160313980 - Meixner; Albert ; et al.	2016-10-27
Energy Efficient Processor Core Architecture For Image Processor App 20160313999 - Meixner; Albert ; et al.	2016-10-27
Architecture For High Performance, Power Efficient, Programmable Image Processing App 20160314555 - Zhu; Qiuling ; et al.	2016-10-27
Two Dimensional Shift Array For Image Processor App 20160316107 - Shacham; Ofer ; et al.	2016-10-27
Line Buffer Unit For Image Processor App 20160316157 - Desai; Neeti ; et al.	2016-10-27
Sheet Generator For Image Processor App 20160316094 - Meixner; Albert ; et al.	2016-10-27
Virtual Linebuffers For Image Signal Processors App 20160219225 - Zhu; Qiuling ; et al.	2016-07-28

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