Fields, Jr.; James Stephen

Patent Applications and Registrations

Patent applications and USPTO patent grants for Fields, Jr.; James Stephen.The latest application filed is for "l2 cache controller with slice directory and unified cache structure".

Company Profile

0.84.5

Fields, Jr.; James Stephen - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Reducing wiring congestion in a cache subsystem utilizing sectored caches with discontiguous addressing Grant 8,433,851 - Clark , et al. April 30, 2	2013-04-30
Apparatus for operating cache-inhibited memory mapped commands to access registers Grant 8,271,738 - Fields, Jr. , et al. September 18, 2	2012-09-18
Data processing system and method for efficient coherency communication utilizing coherency domain indicators Grant 8,230,178 - Fields, Jr. , et al. July 24, 2	2012-07-24
Data processing system and method for efficient coherency communication utilizing coherency domains Grant 8,214,600 - Fields, Jr. , et al. July 3, 2	2012-07-03
Providing low-level hardware access to in-band and out-of-band firmware Grant 8,090,823 - Fields, Jr. , et al. January 3, 2	2012-01-03
L2 cache controller with slice directory and unified cache structure Grant 8,001,330 - Clark , et al. August 16, 2	2011-08-16
Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor Grant 7,916,722 - Fields, Jr. , et al. March 29, 2	2011-03-29
Victim cache using direct intervention Grant 7,827,354 - Clark , et al. November 2, 2	2010-11-02
Efficient coherency communication utilizing an IG coherency state Grant 7,783,841 - Fields, Jr. , et al. August 24, 2	2010-08-24
Efficient storage of metadata in a system memory Grant 7,779,292 - Fields, Jr. , et al. August 17, 2	2010-08-17
Data processing system and method for efficient coherency communication utilizing coherency domain indicators Grant 7,774,555 - Fields, Jr. , et al. August 10, 2	2010-08-10
Recovering from errors in a data processing system Grant 7,707,452 - Cordero , et al. April 27, 2	2010-04-27
Method and apparatus for automatically identifying multiple combinations of operational and non-operational components on integrated circuit chips with a single part number Grant 7,624,318 - Bieswanger , et al. November 24, 2	2009-11-24
Data processing system and method for efficient communication utilizing an Ig coherency state Grant 7,584,329 - Fields, Jr. , et al. September 1, 2	2009-09-01
L2 Cache Controller With Slice Directory And Unified Cache Structure App 20090083489 - Clark; Leo James ; et al.	2009-03-26
Method for Providing Low-Level Hardware Access to In-Band and Out-of-Band Firmware App 20090055563 - Fields, JR.; James Stephen ; et al.	2009-02-26
Reducing Wiring Congestion in a Cache Subsystem Utilizing Sectored Caches with Discontiguous Addressing App 20090049248 - Clark; Leo James ; et al.	2009-02-19
L2 cache controller with slice directory and unified cache structure Grant 7,490,200 - Clark , et al. February 10, 2	2009-02-10
Data processing system and method for efficient communication utilizing an Tn and Ten coherency states Grant 7,480,772 - Fields, Jr. , et al. January 20, 2	2009-01-20
Data processing system and method for efficient storage of metadata in a system memory Grant 7,467,323 - Fields, Jr. , et al. December 16, 2	2008-12-16
Method for providing low-level hardware access to in-band and out-of-band firmware Grant 7,467,204 - Fields, Jr. , et al. December 16, 2	2008-12-16
Method and apparatus for automatic recovery from a failed node concurrent maintenance operation Grant 7,453,816 - Fields, Jr. , et al. November 18, 2	2008-11-18
Data processing system and method for efficient communication utilizing an Tn and Ten coherency states Grant 7,454,577 - Fields, Jr. , et al. November 18, 2	2008-11-18
Dynamic power management via DIMM read operation limiter Grant 7,421,598 - Brittain , et al. September 2, 2	2008-09-02
Method for indirect access to a support interface for memory-mapped resources to reduce system connectivity from out-of-band support processor Grant 7,418,541 - Fields, Jr. , et al. August 26, 2	2008-08-26
System and method for recovering from errors in a data processing system Grant 7,409,580 - Cordero , et al. August 5, 2	2008-08-05
Method to operate cache-inhibited memory mapped commands to access registers Grant 7,392,350 - Fields, Jr. , et al. June 24, 2	2008-06-24
Data Processing System And Method For Efficient Communication Utilizing An Ig Coherency State App 20080052471 - FIELDS, JR.; JAMES STEPHEN ; et al.	2008-02-28
Half-good mode for large L2 cache array topology with different latency domains Grant 7,308,537 - Fields, Jr. , et al. December 11, 2	2007-12-11
Method, system, and program for transferring data directed to virtual memory addresses to a device memory Grant 7,305,526 - Benhase , et al. December 4, 2	2007-12-04
Victim cache using direct intervention Grant 7,305,522 - Clark , et al. December 4, 2	2007-12-04
Modified-invalid cache state to reduce cache-to-cache data transfer operations for speculatively-issued full cache line writes Grant 7,284,097 - Dodson , et al. October 16, 2	2007-10-16
Method to preserve ordering of read and write operations in a DMA system by delaying read access Grant 7,243,194 - Daly, Jr. , et al. July 10, 2	2007-07-10
Method and apparatus for autonomic policy-based thermal management in a data processing system Grant 7,194,645 - Bieswanger , et al. March 20, 2	2007-03-20
Method and apparatus for multiplexing commands in a symmetric multiprocessing system interchip link Grant 7,143,226 - Fields, Jr. , et al. November 28, 2	2006-11-28
Method, system and program product providing a configuration specification language that supports the definition of links between configuration constructs Grant 7,143,387 - Fields, Jr. , et al. November 28, 2	2006-11-28
Apparatus and method for accurately tuning the speed of an integrated circuit Grant 7,116,142 - Ferraiolo , et al. October 3, 2	2006-10-03
Adaptive memory access speculation Grant 7,058,767 - Dodson , et al. June 6, 2	2006-06-06
Method and system for handling multiple bit errors to enhance system reliability Grant 7,007,210 - Fields, Jr. , et al. February 28, 2	2006-02-28
Data processing system and method of communication that employ a request-and-forget protocol Grant 6,970,936 - Fields, Jr. , et al. November 29, 2	2005-11-29
Memory directory management in a multi-node computer system Grant 6,901,485 - Arimilli , et al. May 31, 2	2005-05-31
Dynamic history based mechanism for the granting of exclusive data ownership in a non-uniform memory access (NUMA) computer system Grant 6,886,079 - Arimilli , et al. April 26, 2	2005-04-26
Multi-node data processing system and communication protocol that route write data utilizing a destination ID obtained from a combined response Grant 6,848,003 - Arimilli , et al. January 25, 2	2005-01-25
Method and apparatus for reducing hardware scan dump data Grant 6,832,342 - Fields, Jr. , et al. December 14, 2	2004-12-14
High performance cache intervention mechanism for symmetric multiprocessor systems Grant 6,763,433 - Arimilli , et al. July 13, 2	2004-07-13
Non-uniform memory access (NUMA) data processing system having remote memory cache incorporated within system memory Grant 6,760,809 - Arimilli , et al. July 6, 2	2004-07-06
Method and system for prefetching utilizing memory initiated prefetch write operations Grant 6,760,817 - Arimilli , et al. July 6, 2	2004-07-06
Decentralized global coherency management in a multi-node computer system Grant 6,754,782 - Arimilli , et al. June 22, 2	2004-06-22
Enhanced cache management mechanism via an intelligent system bus monitor Grant 6,721,856 - Arimilli , et al. April 13, 2	2004-04-13
High performance data processing system via cache victimization protocols Grant 6,721,853 - Guthrie , et al. April 13, 2	2004-04-13
Non-uniform memory access (NUMA) data processing system that provides precise notification of remote deallocation of modified data Grant 6,711,652 - Arimilli , et al. March 23, 2	2004-03-23
Enhanced multiprocessor response bus protocol enabling intra-cache line reference exchange Grant 6,704,843 - Arimilli , et al. March 9, 2	2004-03-09
Method and apparatus for allocating data usages within an embedded dynamic random access memory device Grant 6,678,814 - Arimilli , et al. January 13, 2	2004-01-13
Multi-node data processing system having a non-hierarchical interconnect architecture Grant 6,671,712 - Arimilli , et al. December 30, 2	2003-12-30
Non-uniform memory access (NUMA) data processing system having a page table including node-specific data storage and coherency control Grant 6,658,538 - Arimilli , et al. December 2, 2	2003-12-02
Non-uniform memory access (NUMA) computer system having distributed global coherency management Grant 6,654,857 - Arimilli , et al. November 25, 2	2003-11-25
Non-uniform memory access (NUMA) data processing system that provides notification of remote deallocation of shared data Grant 6,633,959 - Arimilli , et al. October 14, 2	2003-10-14
Symmetric multiprocessor address bus protocol with intra-cache line access information Grant 6,631,450 - Arimilli , et al. October 7, 2	2003-10-07
Intelligent cache management mechanism via processor access sequence analysis Grant 6,629,210 - Arimilli , et al. September 30, 2	2003-09-30
Sequencing data on a shared data bus via a memory buffer to prevent data overlap during multiple memory read operations Grant 6,622,222 - Arimilli , et al. September 16, 2	2003-09-16
Two-stage request protocol for accessing remote memory data in a NUMA data processing system Grant 6,615,322 - Arimilli , et al. September 2, 2	2003-09-02
Method and apparatus for accessing banked embedded dynamic random access memory devices Grant 6,606,680 - Arimilli , et al. August 12, 2	2003-08-12
Dynamic cache management in a symmetric multiprocessor system via snoop operation sequence analysis Grant 6,601,144 - Arimilli , et al. July 29, 2	2003-07-29
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers that uses dynamic hardware/software controls Grant 6,601,145 - Arimilli , et al. July 29, 2	2003-07-29
Multiprocessor system bus protocol with group addresses, responses, and priorities Grant 6,591,321 - Arimilli , et al. July 8, 2	2003-07-08
Multi-node data processing system and method of queue management in which a queued operation is speculatively cancelled in response to a partial combined response Grant 6,591,307 - Arimilli , et al. July 8, 2	2003-07-08
Multiprocessor system snoop scheduling mechanism for limited bandwidth snoopers performing directory update Grant 6,546,468 - Arimilli , et al. April 8, 2	2003-04-08
Multi-node data processing system and communication protocol having a partial combined response Grant 6,519,649 - Arimilli , et al. February 11, 2	2003-02-11
High performance data processing system via cache victimization protocols App 20030005232 - Guthrie, Guy Lynn ; et al.	2003-01-02
Reducing resource collisions associated with memory units in a multi-level hierarchy memory system Grant 6,493,814 - Fields, Jr. , et al. December 10, 2	2002-12-10
Programmable agent and method for managing prefetch queues Grant 6,470,427 - Arimilli , et al. October 22, 2	2002-10-22
Method of cache management to dynamically update information-type dependent cache policies Grant 6,434,669 - Arimilli , et al. August 13, 2	2002-08-13
Method of cache management to store information in particular regions of the cache according to information-type Grant 6,434,668 - Arimilli , et al. August 13, 2	2002-08-13
Cache management mechanism to enable information-type dependent cache policies Grant 6,425,058 - Arimilli , et al. July 23, 2	2002-07-23
Data processing system, cache, and method that select a castout victim in response to the latencies of memory copies of cached data Grant 6,408,362 - Arimilli , et al. June 18, 2	2002-06-18
Multiprocessor system in which a cache serving as a highest point of coherency is indicated by a snoop response Grant 6,405,289 - Arimilli , et al. June 11, 2	2002-06-11
Multiprocessor system bus protocol for O state memory-consistent data Grant 6,405,290 - Arimilli , et al. June 11, 2	2002-06-11
Data processing system, cache, and method of cache management including an O state for memory-consistent cache lines Grant 6,397,303 - Arimilli , et al. May 28, 2	2002-05-28
Optimized cache allocation algorithm for multiple speculative requests Grant 6,393,528 - Arimilli , et al. May 21, 2	2002-05-21
Method and system for allocating lower level cache entries for data castout from an upper level cache Grant 6,370,618 - Arimilli , et al. April 9, 2	2002-04-09
Extended cache state with prefetched stream ID information Grant 6,360,299 - Arimilli , et al. March 19, 2	2002-03-19
Method and system for bypassing cache levels when casting out from an upper level cache Grant 6,356,980 - Arimilli , et al. March 12, 2	2002-03-12
High performance mechanism to support O state horizontal cache-to-cache transfers Grant 6,349,368 - Arimilli , et al. February 19, 2	2002-02-19
Method of cache management for dynamically disabling O state memory-consistent data Grant 6,345,341 - Arimilli , et al. February 5, 2	2002-02-05
Multiprocessor system bus with a data-less castout mechanism Grant 6,282,615 - Arimilli , et al. August 28, 2	2001-08-28
High performance multichannel DMA controller for a PCI host bridge with a built-in cache Grant 6,230,219 - Fields, Jr. , et al. May 8, 2	2001-05-08
Configuration access system Grant 6,101,563 - Fields, Jr. , et al. August 8, 2	2000-08-08
Method and apparatus of selecting data transmission channels Grant 6,049,841 - Fields, Jr. , et al. April 11, 2	2000-04-11