Fiedler; Alan S.
Patent Applications and Registrations
Patent applications and USPTO patent grants for Fiedler; Alan S..The latest application filed is for "decision feedback equalization".
- Fiedler; Alan S. - Mountain View CA
- Fiedler; Alan S. - Bloomington MN
- Fiedler; Alan S. - Minneapolis MN
| Patent | Date |
|---|---|
| Serializing transmitter Grant 9,525,573 - Fiedler December 20, 2 | 2016-12-20 |
| Decision feedback equalization Grant 9,455,846 - Fiedler September 27, 2 | 2016-09-27 |
| Serializing transmitter Grant 9,432,061 - Fiedler August 30, 2 | 2016-08-30 |
| Decision Feedback Equalization App 20160248608 - Fiedler; Alan S. | 2016-08-25 |
| Serializing Transmitter App 20160218753 - Fiedler; Alan S. | 2016-07-28 |
| Serializing Transmitter App 20160218896 - Fiedler; Alan S. | 2016-07-28 |
| High-speed I/O data system Grant 9,310,830 - Fiedler April 12, 2 | 2016-04-12 |
| Multi-phase Clock Generation App 20160065196 - Fiedler; Alan S. | 2016-03-03 |
| High-speed I/o Data System App 20140372785 - Fiedler; Alan S. | 2014-12-18 |
| High-speed I/O data system Grant 8,832,487 - Fiedler September 9, 2 | 2014-09-09 |
| Serializing transmitter Grant 8,415,980 - Fiedler April 9, 2 | 2013-04-09 |
| Serializing Transmitter App 20130002300 - Fiedler; Alan S. | 2013-01-03 |
| High-speed I/o Data System App 20130007500 - Fiedler; Alan S. | 2013-01-03 |
| Multiphase clock generator with enhanced phase control Grant 7,821,316 - Fiedler October 26, 2 | 2010-10-26 |
| Multi-phase correction circuit Grant 7,759,997 - Fiedler July 20, 2 | 2010-07-20 |
| Multiphase Clock Generator with Enhanced Phase Control App 20100052744 - Fiedler; Alan S. | 2010-03-04 |
| Multi-phase Correction Circuit App 20090322388 - Fiedler; Alan S. | 2009-12-31 |
| Serial data communication receiver having adaptive termination resistors Grant 6,757,327 - Fiedler June 29, 2 | 2004-06-29 |
| Serial data communication receiver having adaptive equalization Grant 6,731,683 - Fiedler , et al. May 4, 2 | 2004-05-04 |
| Serial data communication receiver having adaptively minimized capture latch offset voltage Grant 6,701,466 - Fiedler March 2, 2 | 2004-03-02 |
| Low-power data serializer Grant 6,417,790 - Fiedler , et al. July 9, 2 | 2002-07-09 |
| Dual-loop PLL with adaptive time constant reduction on first loop Grant 6,054,903 - Fiedler April 25, 2 | 2000-04-25 |
| Dual-loop phase-locked loop Grant 5,854,575 - Fiedler , et al. December 29, 1 | 1998-12-29 |
| Time-division data multiplexer with feedback for clock cross-over adjustment Grant 5,805,089 - Fiedler , et al. September 8, 1 | 1998-09-08 |
| High-swing cascode current mirror Grant 5,680,038 - Fiedler October 21, 1 | 1997-10-21 |
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