| Patent | Date |
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Methods of forming 3-D integrated semiconductor devices having intermediate heat spreading capabilities
Grant 10,014,279 - Werner , et al. July 3, 2 | 2018-07-03 |
Wafer with improved plating current distribution
Grant 9,627,317 - Werner , et al. April 18, 2 | 2017-04-18 |
Semiconductor structure including a die seal leakage detection material, method for the formation thereof and method including a test of a semiconductor structure
Grant 9,455,232 - Werner , et al. September 27, 2 | 2016-09-27 |
Coil Inductor
App 20160260794 - Aubel; Oliver ; et al. | 2016-09-08 |
Wafer With Improved Plating Current Distribution
App 20160240473 - Werner; Thomas ; et al. | 2016-08-18 |
Methods Of Forming 3-d Integrated Semiconductor Devices Having Intermediate Heat Spreading Capabilities
App 20160190104 - Werner; Thomas ; et al. | 2016-06-30 |
Wafer with improved plating current distribution
Grant 9,349,641 - Werner , et al. May 24, 2 | 2016-05-24 |
Semiconductor Structure Including A Die Seal Leakage Detection Material, Method For The Formation Thereof And Method Including A Test Of A Semiconductor Structure
App 20160111381 - Werner; Thomas ; et al. | 2016-04-21 |
3-D integrated semiconductor device comprising intermediate heat spreading capabilities
Grant 9,318,468 - Werner , et al. April 19, 2 | 2016-04-19 |
Wafer With Improved Plating Current Distribution
App 20160079116 - Werner; Thomas ; et al. | 2016-03-17 |
Metallization system of a semiconductor device including metal pillars having a reduced diameter at the bottom
Grant 9,245,860 - Feustel , et al. January 26, 2 | 2016-01-26 |
Embedding metal silicide contact regions reliably into highly doped drain and source regions by a stop implantation
Grant 8,877,597 - Heinrich , et al. November 4, 2 | 2014-11-04 |
Enhancing adhesion of interlayer dielectric materials of semiconductor devices by suppressing silicide formation at the substrate edge
Grant 8,859,398 - Letz , et al. October 14, 2 | 2014-10-14 |
Metallization system of a semiconductor device comprising extra-tapered transition vias
Grant 8,835,303 - Feustel , et al. September 16, 2 | 2014-09-16 |
Restricted stress regions formed in the contact level of a semiconductor device
Grant 8,828,887 - Frohberg , et al. September 9, 2 | 2014-09-09 |
Semiconductor device including ultra low-K (ULK) metallization stacks with reduced chip-package interaction
Grant 8,786,088 - Huisinga , et al. July 22, 2 | 2014-07-22 |
Method for increasing penetration depth of drain and source implantation species for a given gate height
Grant 8,735,237 - Griebenow , et al. May 27, 2 | 2014-05-27 |
Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions
Grant 8,716,126 - Werner , et al. May 6, 2 | 2014-05-06 |
Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging
Grant 8,698,312 - Werking , et al. April 15, 2 | 2014-04-15 |
Reducing copper defects during a wet chemical cleaning of exposed copper surfaces in a metallization layer of a semiconductor device
Grant 8,673,087 - Feustel , et al. March 18, 2 | 2014-03-18 |
Semiconductor Device Comprising Self-aligned Contact Bars And Metal Lines With Increased Via Landing Regions
App 20130154018 - Werner; Thomas ; et al. | 2013-06-20 |
Reducing Patterning Variability Of Trenches In Metallization Layer Stacks With A Low-k Material By Reducing Contamination Of Trench Dielectrics
App 20130130498 - Feustel; Frank ; et al. | 2013-05-23 |
Threshold adjustment for MOS devices by adapting a spacer width prior to implantation
Grant 8,440,534 - Griebenow , et al. May 14, 2 | 2013-05-14 |
Restricted Stress Regions Formed In The Contact Level Of A Semiconductor Device
App 20130084703 - Frohberg; Kai ; et al. | 2013-04-04 |
Semiconductor device comprising self-aligned contact bars and metal lines with increased via landing regions
Grant 8,399,352 - Werner , et al. March 19, 2 | 2013-03-19 |
Sophisticated metallization systems in semiconductors formed by removing damaged dielectric layers after forming the metal features
Grant 8,399,335 - Huisinga , et al. March 19, 2 | 2013-03-19 |
Method of forming a metallization system of a semiconductor device by using a hard mask for defining the via size
Grant 8,377,820 - Werner , et al. February 19, 2 | 2013-02-19 |
Hybrid contact structure with low aspect ratio contacts in a semiconductor device
Grant 8,368,221 - Feustel , et al. February 5, 2 | 2013-02-05 |
Reducing patterning variability of trenches in metallization layer stacks with a low-k material by reducing contamination of trench dielectrics
Grant 8,357,610 - Feustel , et al. January 22, 2 | 2013-01-22 |
Test system and method of reducing damage in seed layers in metallization systems of semiconductor devices
Grant 8,323,989 - Feustel , et al. December 4, 2 | 2012-12-04 |
Built-in compliance in test structures for leakage and dielectric breakdown of dielectric materials of metallization systems of semiconductor devices
Grant 8,314,625 - Aubel , et al. November 20, 2 | 2012-11-20 |
Nano imprint technique with increased flexibility with respect to alignment and feature shaping
Grant 8,293,641 - Seidel , et al. October 23, 2 | 2012-10-23 |
Method For Increasing Penetration Depth Of Drain And Source Implantation Species For A Given Gate Height
App 20120256240 - GRIEBENOW; UWE ; et al. | 2012-10-11 |
Superior Fill Conditions In A Replacement Gate Approach By Using A Tensile Stressed Overlayer
App 20120223388 - Feustel; Frank ; et al. | 2012-09-06 |
Method for increasing penetration depth of drain and source implantation species for a given gate height
Grant 8,241,973 - Griebenow , et al. August 14, 2 | 2012-08-14 |
Method of reducing contamination by providing a removable polymer protection film during microstructure processing
Grant 8,216,927 - Richter , et al. July 10, 2 | 2012-07-10 |
Embedding Metal Silicide Contact Regions Reliably Into Highly Doped Drain and Source Regions by a Stop Implantation
App 20120161210 - Heinrich; Jens ; et al. | 2012-06-28 |
Performance Enhancement in Metallization Systems of Microstructure Devices by Incorporating an Intermediate Barrier Layer
App 20120153479 - Aubel; Oliver ; et al. | 2012-06-21 |
Semiconductor Device Comprising Self-Aligned Contact Bars and Metal Lines With Increased Via Landing Regions
App 20120153366 - Werner; Thomas ; et al. | 2012-06-21 |
Superior fill conditions in a replacement gate approach by using a tensile stressed overlayer
Grant 8,198,147 - Feustel , et al. June 12, 2 | 2012-06-12 |
Local silicidation of via bottoms in metallization systems of semiconductor devices
Grant 8,193,086 - Letz , et al. June 5, 2 | 2012-06-05 |
Unified test structure for stress migration tests
Grant 8,174,010 - Feustel , et al. May 8, 2 | 2012-05-08 |
Method of selectively forming a conductive barrier layer by ALD
Grant 8,173,538 - Feustel , et al. May 8, 2 | 2012-05-08 |
Semiconductor device comprising a carbon-based material for through hole vias
Grant 8,163,594 - Seidel , et al. April 24, 2 | 2012-04-24 |
Method and Semiconductor Device Comprising a Protection Layer for Reducing Stress Relaxation in a Dual Stress Liner Approach
App 20120091535 - FROHBERG; Kai ; et al. | 2012-04-19 |
Providing superior electromigration performance and reducing deterioration of sensitive low-k dielectrics in metallization systems of semiconductor devices
Grant 8,153,524 - Aubel , et al. April 10, 2 | 2012-04-10 |
3-D Integrated Semiconductor Device Comprising Intermediate Heat Spreading Capabilites
App 20120061818 - Werner; Thomas ; et al. | 2012-03-15 |
Method and a semiconductor device comprising a protection layer for reducing stress relaxation in a dual stress liner approach
Grant 8,105,962 - Frohberg , et al. January 31, 2 | 2012-01-31 |
Self-aligned Contact Structure Laterally Enclosed By An Isolation Structure Of A Semiconductor Device
App 20120021581 - Werner; Thomas ; et al. | 2012-01-26 |
Sophisticated Metallization Systems in Semiconductors Formed by Removing Damaged Dielectric Surface Layers After Forming the Metal Features
App 20120001343 - Huisinga; Torsten ; et al. | 2012-01-05 |
Semiconductor Device Including Ultra Low-K (ULK) Metallization Stacks with Reduced Chip-Package Interaction
App 20120001323 - Huisinga; Torsten ; et al. | 2012-01-05 |
3-D integrated semiconductor device comprising intermediate heat spreading capabilities
Grant 8,080,866 - Werner , et al. December 20, 2 | 2011-12-20 |
Method for patterning a metallization layer by reducing resist strip induced damage of the dielectric material
Grant 8,048,811 - Feustel , et al. November 1, 2 | 2011-11-01 |
Semiconductor device comprising a capacitor in the metallization system and a method of forming the capacitor
Grant 8,048,736 - Werner , et al. November 1, 2 | 2011-11-01 |
Method of reducing non-uniformities during chemical mechanical polishing of excess metal in a metallization level of microstructure devices
Grant 8,039,398 - Feustel , et al. October 18, 2 | 2011-10-18 |
Method and test structure for estimating focus settings in a lithography process based on CD measurements
Grant 8,040,497 - Werner , et al. October 18, 2 | 2011-10-18 |
Semiconductor Device Comprising a Capacitor in the Metallization System Formed by a Hard Mask Patterning Regime
App 20110241167 - Feustel; Frank ; et al. | 2011-10-06 |
Enhancing structural integrity of low-k dielectrics in metallization systems of semiconductor devices by using a crack suppressing material layer
Grant 8,030,209 - Werner , et al. October 4, 2 | 2011-10-04 |
Threshold Adjustment For Mos Devices By Adapting A Spacer Width Prior To Implantation
App 20110223732 - Griebenow; Uwe ; et al. | 2011-09-15 |
Method of Reducing Contamination by Providing a Removable Polymer Protection Film During Microstructure Processing
App 20110201135 - Richter; Ralf ; et al. | 2011-08-18 |
Technique for reducing plasma-induced etch damage during the formation of vias in interlayer dielectrics
Grant 7,989,352 - Feustel , et al. August 2, 2 | 2011-08-02 |
Fabricating vias of different size of a semiconductor device by splitting the via patterning process
Grant 7,977,237 - Feustel , et al. July 12, 2 | 2011-07-12 |
Method of reducing contamination by providing a removable polymer protection film during microstructure processing
Grant 7,955,962 - Richter , et al. June 7, 2 | 2011-06-07 |
Nano Imprint Technique With Increased Flexibility With Respect To Alignment And Feature Shaping
App 20110117723 - Seidel; Robert ; et al. | 2011-05-19 |
Fabricating Vias Of Different Size Of A Semiconductor Device By Splitting The Via Patterning Process
App 20110104867 - Feustel; Frank ; et al. | 2011-05-05 |
Field effect transistor having a stressed contact etch stop layer with reduced conformality
Grant 7,932,166 - Frohberg , et al. April 26, 2 | 2011-04-26 |
Nano imprint technique with increased flexibility with respect to alignment and feature shaping
Grant 7,928,004 - Seidel , et al. April 19, 2 | 2011-04-19 |
Reducing contamination of semiconductor substrates during beol processing by providing a protection layer at the substrate edge
Grant 7,915,170 - Ruo Qing , et al. March 29, 2 | 2011-03-29 |
Technique for forming an interlayer dielectric material of increased reliability above a structure including closely spaced lines
Grant 7,910,496 - Feustel , et al. March 22, 2 | 2011-03-22 |
Superior Fill Conditions In A Replacement Gate Approach By Using A Tensile Stressed Overlayer
App 20110049640 - Feustel; Frank ; et al. | 2011-03-03 |
Recessed Interlayer Dielectric In A Metallization Structure Of A Semiconductor Device
App 20110049727 - Aubel; Oliver ; et al. | 2011-03-03 |
Semiconductor structure comprising an electrically conductive feature and method of forming a semiconductor structure
Grant 7,879,709 - Feustel , et al. February 1, 2 | 2011-02-01 |
High-aspect Ratio Contact Element With Superior Shape In A Semiconductor Device For Improving Liner Deposition
App 20100301486 - Frohberg; Kai ; et al. | 2010-12-02 |
Enhanced Electromigration Performance Of Copper Lines In Metallization Systems Of Semiconductor Devices By Surface Alloying
App 20100289125 - Feustel; Frank ; et al. | 2010-11-18 |
Enhancing Adhesion Of Interlayer Dielectric Materials Of Semiconductor Devices By Suppressing Silicide Formation At The Substrate Edge
App 20100248463 - Letz; Tobias ; et al. | 2010-09-30 |
Test System And Method Of Reducing Damage In Seed Layers In Metallization Systems Of Semiconductor Devices
App 20100244028 - Feustel; Frank ; et al. | 2010-09-30 |
Test structure for OPC-related shorts between lines in a semiconductor device
Grant 7,800,106 - Feustel , et al. September 21, 2 | 2010-09-21 |
Metallization System Of A Semiconductor Device Including Metal Pillars Having A Reduced Diameter At The Bottom
App 20100219527 - Feustel; Frank ; et al. | 2010-09-02 |
Providing Superior Electromigration Performance And Reducing Deterioration Of Sensitive Low-k Dielectrics In Metallization Systems Of Semiconductor Devices
App 20100221911 - Aubel; Oliver ; et al. | 2010-09-02 |
Method Of Forming A Metallization System Of A Semiconductor Device By Using A Hard Mask For Defining The Via Size
App 20100197133 - Werner; Thomas ; et al. | 2010-08-05 |
Test structure for monitoring leakage currents in a metallization layer
Grant 7,764,078 - Feustel , et al. July 27, 2 | 2010-07-27 |
Metallization System Of A Semiconductor Device Comprising Extra-tapered Transition Vias
App 20100164121 - Feustel; Frank ; et al. | 2010-07-01 |
Local Silicidation Of Via Bottoms In Metallization Systems Of Semiconductor Devices
App 20100164123 - Letz; Tobias ; et al. | 2010-07-01 |
Method for preventing the formation of electrical shorts via contact ILD voids
Grant 7,741,191 - Frohberg , et al. June 22, 2 | 2010-06-22 |
Built-in Compliance In Test Structures For Leakage And Dielectric Breakdown Of Dielectric Materials Of Metallization Systems Of Semiconductor Devices
App 20100134125 - Aubel; Oliver ; et al. | 2010-06-03 |
Microstructure Device Including A Metallization Structure With Air Gaps Formed Commonly With Vias
App 20100133699 - Werner; Thomas ; et al. | 2010-06-03 |
Restricted Stress Regions Formed In The Contact Level Of A Semiconductor Device
App 20100133621 - Frohberg; Kai ; et al. | 2010-06-03 |
Performance Enhancement In Metallization Systems Of Microstructure Devices By Incorporating Grain Size Increasing Metal Features
App 20100133700 - Werner; Thomas ; et al. | 2010-06-03 |
Test structure for estimating electromigration effects with increased robustness with respect to barrier defects in vias
Grant 7,705,352 - Feustel , et al. April 27, 2 | 2010-04-27 |
Using A Cap Layer In Metallization Systems Of Semiconductor Devices As A Cmp And Etch Stop Layer
App 20100052181 - Werner; Thomas ; et al. | 2010-03-04 |
3-d Integrated Semiconductor Device Comprising Intermediate Heat Spreading Capabilities
App 20100052134 - Werner; Thomas ; et al. | 2010-03-04 |
Semiconductor Device Comprising A Carbon-based Material For Through Hole Vias
App 20100052110 - Seidel; Robert ; et al. | 2010-03-04 |
Enhancing Structural Integrity Of Low-k Dielectrics In Metallization Systems Of Semiconductor Devices By Using A Crack Suppressing Material Layer
App 20100055903 - WERNER; Thomas ; et al. | 2010-03-04 |
Threshold adjustment for MOS devices by adapting a spacer width prior to implantation
App 20090321850 - Griebenow; Uwe ; et al. | 2009-12-31 |
Reduction Of Metal Silicide Diffusion In A Semiconductor Device By Protecting Sidewalls Of An Active Region
App 20090294809 - Frohberg; Kai ; et al. | 2009-12-03 |
Microstructure Device Including A Metallization Structure With Self-aligned Air Gaps Between Closely Spaced Metal Lines
App 20090294898 - Feustel; Frank ; et al. | 2009-12-03 |
Method For Reducing Metal Irregularities In Advanced Metallization Systems Of Semiconductor Devices
App 20090298279 - Feustel; Frank ; et al. | 2009-12-03 |
Reducing Patterning Variability Of Trenches In Metallization Layer Stacks With A Low-k Material By Reducing Contamination Of Trench Dielectrics
App 20090243116 - Feustel; Frank ; et al. | 2009-10-01 |
Method For Patterning A Metallization Layer By Reducing Resist Strip Induced Damage Of The Dielectric Material
App 20090246951 - Feustel; Frank ; et al. | 2009-10-01 |
Method For Increasing Penetration Depth Of Drain And Source Implantation Species For A Given Gate Height
App 20090221123 - Griebenow; Uwe ; et al. | 2009-09-03 |
Self-aligned Contact Structure In A Semiconductor Device
App 20090194825 - Werner; Thomas ; et al. | 2009-08-06 |
Semiconductor Device Comprising A Capacitor In The Metallization System And A Method Of Forming The Capacitor
App 20090194845 - Werner; Thomas ; et al. | 2009-08-06 |
Semiconductor Structure Comprising An Electrical Connection And Method Of Forming The Same
App 20090181537 - SEIDEL; ROBERT ; et al. | 2009-07-16 |
Method And A Semiconductor Device Comprising A Protection Layer For Reducing Stress Relaxation In A Dual Stress Liner Approach
App 20090140348 - Frohberg; Kai ; et al. | 2009-06-04 |
Hybrid Contact Structure With Low Aspect Ratio Contacts In A Semiconductor Device
App 20090140431 - Feustel; Frank ; et al. | 2009-06-04 |
Reducing Copper Defects During A Wet Chemical Cleaning Of Exposed Copper Surfaces In A Metallization Layer Of A Semiconductor Device
App 20090139543 - Feustel; Frank ; et al. | 2009-06-04 |
Dual Integration Scheme For Low Resistance Metal Layers
App 20090108462 - Peters; Carsten ; et al. | 2009-04-30 |
Semiconductor Structure Comprising An Electrically Conductive Feature And Method Of Forming A Semiconductor Structure
App 20090085145 - Feustel; Frank ; et al. | 2009-04-02 |
Sidewall Protection Layer
App 20090085173 - Boemmels; Juergen ; et al. | 2009-04-02 |
Semiconductor Device Having A Locally Enhanced Electromigration Resistance In An Interconnect Structure
App 20090032961 - Feustel; Frank ; et al. | 2009-02-05 |
Technique For Forming An Interlayer Dielectric Material Of Increased Reliability Above A Structure Including Closely Spaced Lines
App 20090001526 - Feustel; Frank ; et al. | 2009-01-01 |
Method of forming an etch indicator layer for reducing etch non-uniformities
Grant 7,462,563 - Feustel , et al. December 9, 2 | 2008-12-09 |
Semiconductor Structure Comprising An Electrical Connection And Method Of Forming The Same
App 20080265426 - Seidel; Robert ; et al. | 2008-10-30 |
Unified Test Structure For Stress Migration Tests
App 20080265247 - Feustel; Frank ; et al. | 2008-10-30 |
Method For Preventing The Formation Of Electrical Shorts Via Contact Ild Voids
App 20080265365 - Frohberg; Kai ; et al. | 2008-10-30 |
Semiconductor Structure Comprising An Electrically Conductive Feature And Method Of Forming The Same
App 20080265419 - Frohberg; Kai ; et al. | 2008-10-30 |
Method Of Reducing Non-uniformities During Chemical Mechanical Polishing Of Excess Metal In A Metallization Level Of Microstructure Devices
App 20080206994 - Feustel; Frank ; et al. | 2008-08-28 |
Method For The Protection Of Metal Layers Against External Contamination
App 20080160762 - Feustel; Frank ; et al. | 2008-07-03 |
Test Structure For Estimating Electromigration Effects With Increased Robustness With Respect To Barrier Defects In Vias
App 20080157075 - Feustel; Frank ; et al. | 2008-07-03 |
Method And Test Structure For Estimating Focus Settings In A Lithography Process Based On Cd Measurements
App 20080131796 - Werner; Thomas ; et al. | 2008-06-05 |
System And Method For Reducing Collateral Transport-induced Damage During Microstructure Processing
App 20080131257 - Peters; Carsten ; et al. | 2008-06-05 |
Method Of Selectively Forming A Conductive Barrier Layer By Ald
App 20080132057 - Feustel; Frank ; et al. | 2008-06-05 |
Test Structure For Opc-related Shorts Between Lines In A Semiconductor Device
App 20080099761 - Feustel; Frank ; et al. | 2008-05-01 |
Technique For Reducing Plasma-induced Etch Damage During The Formation Of Vias In Interlayer Dielectrics
App 20080057705 - Feustel; Frank ; et al. | 2008-03-06 |
Field Effect Transistor Having A Stressed Contact Etch Stop Layer With Reduced Conformality
App 20080054314 - Frohberg; Kai ; et al. | 2008-03-06 |
Method Of Forming An Etch Indicator Layer For Reducing Etch Non-uniformities
App 20080026487 - Feustel; Frank ; et al. | 2008-01-31 |
Method Of Reducing Contamination By Providing A Removable Polymer Protection Film During Microstructure Processing
App 20080026492 - Richter; Ralf ; et al. | 2008-01-31 |
Nano Imprint Technique With Increased Flexibility With Respect To Alignment And Feature Shaping
App 20080003818 - Seidel; Robert ; et al. | 2008-01-03 |
Reducing Contamination Of Semiconductor Substrates During Beol Processing By Providing A Protection Layer At The Substrate Edge
App 20080003830 - Qing; Su Ruo ; et al. | 2008-01-03 |
Method For Increasing The Planarity Of A Surface Topography In A Microstructure
App 20080003826 - Werner; Thomas ; et al. | 2008-01-03 |
Test Structure For Monitoring Leakage Currents In A Metallization Layer
App 20070296439 - Feustel; Frank ; et al. | 2007-12-27 |
Technique for enhancing thermal and mechanical characteristics of an underfill material of a substrate/die assembly
Grant 7,306,976 - Feustel , et al. December 11, 2 | 2007-12-11 |
Method And Test Structure For Estimating Electromigration Effects Caused By Porous Barrier Materials
App 20070278484 - Feustel; Frank ; et al. | 2007-12-06 |
Technique for forming copper-containing lines embedded in a low-k dielectric by providing a stiffening layer
App 20060267201 - Huebler; Peter ; et al. | 2006-11-30 |
Method of forming electrically conductive lines in an integrated circuit
App 20060267207 - Feustel; Frank ; et al. | 2006-11-30 |
Technique for enhancing thermal and mechanical characteristics of an underfill material of a substrate/die assembly
App 20060246627 - Feustel; Frank ; et al. | 2006-11-02 |
Semiconductor device including a hybrid metallization layer stack for enhanced mechanical strength during and after packaging
App 20050242435 - Werking, James ; et al. | 2005-11-03 |
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