| Patent | Date |
|---|
Forming Vias In A Semiconductor Device
App 20210313217 - Kumar; Kaushik ; et al. | 2021-10-07 |
Method of selective deposition for BEOL dielectric etch
Grant 11,087,973 - Feurprier , et al. August 10, 2 | 2021-08-10 |
Semiconductor Device Manufacturing Method
App 20210118727 - YATSUDA; Koichi ; et al. | 2021-04-22 |
Semiconductor device manufacturing method
Grant 10,910,259 - Yatsuda , et al. February 2, 2 | 2021-02-02 |
Semiconductor Device Manufacturing Method
App 20190181039 - YATSUDA; Koichi ; et al. | 2019-06-13 |
Method Of Selective Deposition For Beol Dielectric Etch
App 20180174897 - Feurprier; Yannick ; et al. | 2018-06-21 |
Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP)
Grant 9,818,610 - Matsumoto , et al. November 14, 2 | 2017-11-14 |
Self aligned via in integrated circuit
Grant 9,768,113 - Feurprier , et al. September 19, 2 | 2017-09-19 |
Trench And Hole Patterning With Euv Resists Using Dual Frequency Capacitively Coupled Plasma (ccp)
App 20170263443 - Matsumoto; Hiroie ; et al. | 2017-09-14 |
Trench and hole patterning with EUV resists using dual frequency capacitively coupled plasma (CCP)
Grant 9,607,834 - Matsumoto , et al. March 28, 2 | 2017-03-28 |
Self Aligned Via In Integrated Circuit
App 20160379929 - Feurprier; Yannick ; et al. | 2016-12-29 |
Trench And Hole Patterning With Euv Resists Using Dual Frequency Capacitively Coupled Plasma (ccp)
App 20160293405 - Matsumoto; Hiroie ; et al. | 2016-10-06 |
Self aligned via in integrated circuit
Grant 9,385,078 - Feurprier , et al. July 5, 2 | 2016-07-05 |
Self aligned via in integrated circuit
Grant 9,373,582 - Feurprier , et al. June 21, 2 | 2016-06-21 |
Integrated Circuit Via Structure And Method Of Fabrication
App 20150076707 - Mignot; Yann ; et al. | 2015-03-19 |
Dry etching method for metallization pattern profiling
Grant 8,809,185 - Feurprier August 19, 2 | 2014-08-19 |
Method to remove capping layer of insulation dielectric in interconnect structures
Grant 8,202,803 - Feurprier , et al. June 19, 2 | 2012-06-19 |
Method for metallizing a pattern in a dielectric film
Grant 8,080,473 - Feurprier December 20, 2 | 2011-12-20 |
Method to remove capping layer of insulation dielectric in interconnect structures
App 20110143542 - FEURPRIER; Yannick ; et al. | 2011-06-16 |
Method for etching low-k material using an oxide hard mask
Grant 7,947,609 - Feurprier May 24, 2 | 2011-05-24 |
Method for forming a damascene structure
Grant 7,935,640 - Feurprier May 3, 2 | 2011-05-03 |
Method for selective removal of damaged multi-stack bilayer films
Grant 7,723,237 - Hyland , et al. May 25, 2 | 2010-05-25 |
Low damage method for ashing a substrate using CO.sub.2/CO-based process
Grant 7,637,269 - Zin , et al. December 29, 2 | 2009-12-29 |
Method for metallizing a pattern in a dielectric film
App 20090061634 - Feurprier; Yannick | 2009-03-05 |
Method for etching low-k material using an oxide hard mask
App 20090042398 - FEURPRIER; Yannick | 2009-02-12 |
Method for forming a damascene structure
App 20090039518 - Feurprier; Yannick | 2009-02-12 |
Method For Selective Removal Of Damaged Multi-stack Bilayer Films
App 20080142988 - Hyland; Sandra ; et al. | 2008-06-19 |
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