Ferreira; Paul

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ferreira; Paul.The latest application filed is for "device and method for alignment of vertically stacked wafers and die".

Company Profile

2.14.12

Ferreira; Paul - Barraux FR
Ferreira; Paul - Lagrangeville NY US
Ferreira; Paul - Goucelin FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Device and method for alignment of vertically stacked wafers and die Grant 11,205,621 - Zhang , et al. December 21, 2	2021-12-21
Device And Method For Alignment Of Vertically Stacked Wafers And Die App 20200203286 - ZHANG; John H. ; et al.	2020-06-25
Device and method for alignment of vertically stacked wafers and die Grant 10,615,125 - Zhang , et al.	2020-04-07
Device And Method For Alignment Of Vertically Stacked Wafers And Die App 20180114756 - ZHANG; John H. ; et al.	2018-04-26
Device and method for alignment of vertically stacked wafers and die Grant 9,870,999 - Zhang , et al. January 16, 2	2018-01-16
Device and method for alignment of vertically stacked wafers and die Grant 9,324,660 - Zhang , et al. April 26, 2	2016-04-26
Device And Method For Alignment Of Vertically Stacked Wafers And Die App 20160079131 - ZHANG; John H. ; et al.	2016-03-17
Method for protecting the gate of a transistor and corresponding integrated circuit Grant 8,823,107 - Ferreira September 2, 2	2014-09-02
Device And Method For Alignment Of Vertically Stacked Wafers And Die App 20140027933 - Zhang; John H. ; et al.	2014-01-30
CMP techniques for overlapping layer removal Grant 8,603,916 - Zhang , et al. December 10, 2	2013-12-10
Device and method for alignment of vertically stacked wafers and die Grant 8,569,899 - Zhang , et al. October 29, 2	2013-10-29
Precise Real Time And Position Low Pressure Control Of Chemical Mechanical Polish (cmp) Head App 20120122373 - Zhang; John H. ; et al.	2012-05-17
Cmp Techniques For Overlapping Layer Removal App 20110156152 - Zhang; John H. ; et al.	2011-06-30
Device And Method For Alignment Of Vertically Stacked Wafers And Die App 20110156284 - Zhang; John H. ; et al.	2011-06-30
Method For Protecting The Gate Of A Transistor And Corresponding Integrated Circuit App 20110057264 - Ferreira; Paul	2011-03-10
Method for protecting the gate of a transistor and corresponding integrated circuit Grant 7,838,407 - Ferreira November 23, 2	2010-11-23
Method for protecting the gate of a transistor and corresponding integrated circuit App 20070051971 - Ferreira; Paul	2007-03-08
Method for forming contact openings on a MOS integrated circuit Grant 6,911,366 - Ferreira , et al. June 28, 2	2005-06-28
Method for forming contact openings on a MOS integrated circuit App 20040212095 - Ferreira, Paul ; et al.	2004-10-28
Process for treating complementary regions of the surface of a substrate and semiconductor product obtained by this process Grant 6,797,597 - Ferreira , et al. September 28, 2	2004-09-28
Method for production process for the local interconnection level using a dielectric conducting pair on pair Grant 6,689,655 - Coronel , et al. February 10, 2	2004-02-10
Process for treating complementary regions of the surface of a substrate and semiconductor product obtained by this process App 20030016571 - Ferreira, Paul ; et al.	2003-01-23
Production process for the local interconnection level using a dielectric-conducting pair on grid App 20020142519 - Coronel, Philippe ; et al.	2002-10-03

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