Ferrant; Richard

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ferrant; Richard.The latest application filed is for "memory device with dynamically operated reference circuits".

Company Profile

0.77.65

Ferrant; Richard - Esquibien FR
Ferrant; Richard - Crolles FR
Ferrant; Richard - Saint Ismier FR
Ferrant, Richard - Esquibien Finistere
Ferrant, Richard - Suguensau FR
Ferrant, Richard - US
Ferrant; Richard - Carrollton TX
Ferrant; Richard - Le Fontanil Cornillon FR
Ferrant; Richard - Aix En Provence FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Look-up table architecture Grant 10,110,235 - Ferrant October 23, 2	2018-10-23
Look-up table Grant 9,621,168 - Ferrant April 11, 2	2017-04-11
Memory device with dynamically operated reference circuits Grant 9,576,642 - Thewes , et al. February 21, 2	2017-02-21
Pseudo-inverter circuit with multiple independent gate transistors Grant 9,496,877 - Mazure , et al. November 15, 2	2016-11-15
Device having a contact between semiconductor regions through a buried insulating layer, and process for fabricating said device Grant 9,490,264 - Mazure , et al. November 8, 2	2016-11-08
Tristate gate Grant 9,479,174 - Ferrant October 25, 2	2016-10-25
Circuit and method for sensing a difference in voltage on a pair of dual signal lines, in particular through equalize transistor Grant 9,390,771 - Ferrant , et al. July 12, 2	2016-07-12
Memory Device With Dynamically Operated Reference Circuits App 20160086652 - Thewes; Roland ; et al.	2016-03-24
Sense amplifier with dual gate precharge and decode transistors Grant 9,251,871 - Ferrant , et al. February 2, 2	2016-02-02
Eprom cell Grant 9,230,662 - Ferrant January 5, 2	2016-01-05
Charge pump circuit comprising multiple--gate transistors and method of operating the same Grant 9,225,237 - Ferrant December 29, 2	2015-12-29
Semiconductor memory having staggered sense amplifiers associated with a local column decoder Grant 9,159,400 - Ferrant , et al. October 13, 2	2015-10-13
Charge Pump Circuit Comprising Multiple - Gate Transistors And Method Of Operating The Same App 20150263610 - Ferrant; Richard	2015-09-17
Differential sense amplifier without switch transistors Grant 9,135,964 - Ferrant , et al. September 15, 2	2015-09-15
Differential sense amplifier without dedicated precharge transistors Grant 9,111,593 - Ferrant , et al. August 18, 2	2015-08-18
Complementary Fet Injection For A Floating Body Cell App 20150145049 - Hoffman; Franz ; et al.	2015-05-28
Method for manufacturing a semiconductor substrate Grant 9,035,474 - Mazure , et al. May 19, 2	2015-05-19
Eprom Cell App 20150042381 - Ferrant; Richard	2015-02-12
Differential sense amplifier without dedicated pass-gate transistors Grant 8,953,399 - Ferrant , et al. February 10, 2	2015-02-10
Look-up Table Architecture App 20150035562 - Ferrant; Richard	2015-02-05
Multiplexer, Look-up Table And Fpga App 20150028920 - Ferrant; Richard	2015-01-29
Look-up Table App 20150022237 - Ferrant; Richard	2015-01-22
Circuit And Method For Sensing A Difference In Voltage On A Pair Of Dual Signal Lines, In Particular Through Equalize Transistor App 20140376318 - Ferrant; Richard ; et al.	2014-12-25
Tristate Gate App 20140340118 - Ferrant; Richard	2014-11-20
Sense Amplifier With Dual Gate Precharge And Decode Transistors App 20140321225 - Ferrant; Richard ; et al.	2014-10-30
Pseudo-inverter Circuit With Multiple Independent Gate Transistors App 20140225648 - Mazure; Carlos ; et al.	2014-08-14
Flash memory cell on SeOI having a second control gate buried under the insulating layer Grant 8,664,712 - Mazure , et al. March 4, 2	2014-03-04
Multi-layer structures and process for fabricating semiconductor devices Grant 8,652,887 - Nguyen , et al. February 18, 2	2014-02-18
Pseudo-inverter circuit on SeOI Grant 8,654,602 - Mazure , et al. February 18, 2	2014-02-18
Nano-sense amplifier Grant 8,625,374 - Mazure , et al. January 7, 2	2014-01-07
SRAM-type memory cell Grant 8,575,697 - Mazure , et al. November 5, 2	2013-11-05
Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer Grant 8,508,289 - Mazure , et al. August 13, 2	2013-08-13
Device comprising a field-effect transistor in a silicon-on-insulator Grant 8,455,938 - Nguyen , et al. June 4, 2	2013-06-04
Data-path cell on an SeOI substrate with a back control gate beneath the insulating layer Grant 8,432,216 - Mazure , et al. April 30, 2	2013-04-30
Nano-sense Amplifier App 20130100749 - MAZURE; Carlos ; et al.	2013-04-25
Arrays of transistors with back control gates buried beneath the insulating film of a semiconductor-on-insulator substrate Grant 8,384,425 - Mazure , et al. February 26, 2	2013-02-26
Nano-sense amplifier Grant 8,358,552 - Mazure , et al. January 22, 2	2013-01-22
Devices and methods for comparing data in a content-addressable memory Grant 8,325,506 - Mazure , et al. December 4, 2	2012-12-04
MRAM device structure employing thermally-assisted write operations and thermally-unassisted self-referencing operations Grant 8,310,866 - Leuschner , et al. November 13, 2	2012-11-13
Memory cell with a channel buried beneath a dielectric layer Grant 8,304,833 - Mazure , et al. November 6, 2	2012-11-06
DRAM memory cell having a vertical bipolar injector Grant 8,305,803 - Mazure , et al. November 6, 2	2012-11-06
Differential Sense Amplifier Without Dedicated Pass-gate Transistors App 20120275253 - Ferrant; Richard ; et al.	2012-11-01
Differential Sense Amplifier Without Switch Transistors App 20120275252 - Ferrant; Richard ; et al.	2012-11-01
Differential Sense Amplifier Without Dedicated Precharge Transistors App 20120275254 - Ferrant; Richard ; et al.	2012-11-01
PSEUDO-INVERTER CIRCUIT ON SeOI App 20120250444 - Mazure; Carlos ; et al.	2012-10-04
Semiconductor Memory Having Staggered Sense Amplifiers Associated With A Local Column Decoder App 20120243360 - Ferrant; Richard ; et al.	2012-09-27
Multi-layer Structures And Process For Fabricating Semiconductor Devices App 20120231606 - Nguyen; Bich-Yen ; et al.	2012-09-13
Bus with error correction circuitry Grant 8,266,494 - Ferrant , et al. September 11, 2	2012-09-11
Pseudo-inverter circuit on SeOI Grant 8,223,582 - Mazure , et al. July 17, 2	2012-07-17
Device Comprising A Field-effect Transistor In A Silicon-on-insulator App 20110260233 - Nguyen; Bich-Yen ; et al.	2011-10-27
PSEUDO-INVERTER CIRCUIT ON SeO1 App 20110242926 - Mazure; Carlos ; et al.	2011-10-06
Method For Manufacturing A Semiconductor Substrate App 20110241157 - Mazure; Carlos ; et al.	2011-10-06
Sram-type Memory Cell App 20110233675 - Mazure; Carlos ; et al.	2011-09-29
Nano-sense Amplifier App 20110222361 - Mazure; Carlos ; et al.	2011-09-15
DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER App 20110215860 - Mazure; Carlos ; et al.	2011-09-08
Integrated circuit comprising a transistor and a capacitor, and fabrication method Grant 7,994,560 - Caillat , et al. August 9, 2	2011-08-09
Device Having A Contact Between Semiconductor Regions Through A Buried Insulating Layer, And Process For Fabricating Said Device App 20110169090 - Mazure; Carlos ; et al.	2011-07-14
Dram Memory Cell Having A Vertical Bipolar Injector App 20110170343 - Mazure; Carlos ; et al.	2011-07-14
Devices And Methods For Comparing Data In A Content-addressable Memory App 20110170327 - Mazure; Carlos ; et al.	2011-07-14
Memory Cell With A Channel Buried Beneath A Dielectric Layer App 20110169087 - MAZURE; CARLOS ; et al.	2011-07-14
METHOD OF CONTROLLING A DRAM MEMORY CELL ON THE SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER App 20110134690 - Mazure; Carlos ; et al.	2011-06-09
Arrays Of Transistors With Back Control Gates Buried Beneath The Insulating Film Of A Semiconductor-on-insulator Substrate App 20110133776 - Mazure; Carlos ; et al.	2011-06-09
DATA-PATH CELL ON AN SeOI SUBSTRATE WITH A BACK CONTROL GATE BENEATH THE INSULATING LAYER App 20110133822 - Mazure; Carlos ; et al.	2011-06-09
FLASH MEMORY CELL ON SeOI HAVING A SECOND CONTROL GATE BURIED UNDER THE INSULATING LAYER App 20110134698 - Mazure; Carlos ; et al.	2011-06-09
Semiconductor array including a matrix of cells and a method of making a semiconductor array having a matrix of cells Grant 7,817,466 - Ferrant , et al. October 19, 2	2010-10-19
Semiconductor memory device and method of operating same Grant 7,733,693 - Ferrant , et al. June 8, 2	2010-06-08
MRAM Device Structure Employing Thermally-Assisted Write Operations and Thermally-Unassisted Self-Referencing Operations App 20100002501 - Leuschner; Rainer ; et al.	2010-01-07
Integrated Circuit Comprising A Transistor And A Capacitor, And Fabrication Method App 20090121269 - Caillat; Christian ; et al.	2009-05-14
Bus With Error Correction Circuitry App 20090125789 - Ferrant; Richard ; et al.	2009-05-14
Semiconductor Array App 20090086535 - Ferrant; Richard ; et al.	2009-04-02
Manufacturing method for homogenizing the environment of transistors and associated device App 20080251848 - Borot; Bertrand ; et al.	2008-10-16
Semiconductor memory device and method of operating same App 20080205114 - Ferrant; Richard ; et al.	2008-08-28
Semiconductor memory device and method of operating same Grant 7,359,229 - Ferrant , et al. April 15, 2	2008-04-15
Semiconductor memory device and method of operating same App 20070159911 - Ferrant; Richard ; et al.	2007-07-12
Resistive memory cell random access memory device and method of fabrication Grant 7,212,432 - Ferrant , et al. May 1, 2	2007-05-01
MRAM with vertical storage element and field sensor Grant 7,200,032 - Braun , et al. April 3, 2	2007-04-03
High-density high current device cell App 20070069296 - Park; Human ; et al.	2007-03-29
Semiconductor memory device and method of operating same Grant 7,187,581 - Ferrant , et al. March 6, 2	2007-03-06
MRAM storage device Grant 7,180,160 - Ferrant , et al. February 20, 2	2007-02-20
Memory circuit with shared redundancy Grant 7,180,801 - Ferrant , et al. February 20, 2	2007-02-20
DRAM refreshment Grant 7,161,863 - Ferrant , et al. January 9, 2	2007-01-09
Content addressable memory cell including resistive memory elements Grant 7,130,206 - Ferrant October 31, 2	2006-10-31
Semiconductor memory cell, array, architecture and device, and method of operating same Grant 7,085,153 - Ferrant , et al. August 1, 2	2006-08-01
Semiconductor memory device and method of operating same Grant 7,085,156 - Ferrant , et al. August 1, 2	2006-08-01
Resistive memory cell configuration and method for sensing resistance values Grant 7,068,533 - Ferrant , et al. June 27, 2	2006-06-27
Small size ROM Grant 7,057,916 - Ferrant June 6, 2	2006-06-06
Resistive Memory Cell Configuration And Method For Sensing Resistance Values App 20060067103 - Ferrant; Richard ; et al.	2006-03-30
Resistive memory cell random access memory device and method of fabrication App 20060067112 - Ferrant; Richard ; et al.	2006-03-30
Content addressable memory cell including resistive memory elements App 20060067098 - Ferrant; Richard	2006-03-30
MRAM with vertical storage element and field sensor App 20060039187 - Braun; Daniel ; et al.	2006-02-23
Cache cell with masking Grant 6,995,997 - Ferrant February 7, 2	2006-02-07
MRAM storage device App 20060024886 - Ferrant; Richard ; et al.	2006-02-02
Memory circuit with dynamic redundancy Grant 6,934,202 - Ferrant August 23, 2	2005-08-23
Semiconductor memory device and method of operating same App 20050174873 - Ferrant, Richard ; et al.	2005-08-11
DRAM refreshment App 20050157534 - Ferrant, Richard ; et al.	2005-07-21
Semiconductor memory device and method of operating same App 20050157580 - Ferrant, Richard ; et al.	2005-07-21
Amplifier for reading storage cells with exclusive-OR type function Grant 6,920,075 - Ferrant July 19, 2	2005-07-19
Memory circuit with shared redundancy App 20050146952 - Ferrant, Richard ; et al.	2005-07-07
Semiconductor memory cell, array, architecture and device, and method of operating same App 20050013163 - Ferrant, Richard ; et al.	2005-01-20
Small size ROM App 20040264228 - Ferrant, Richard	2004-12-30
Cache cell with masking App 20040252536 - Ferrant, Richard	2004-12-16
Semiconductor memory device and method of operating same App 20040228168 - Ferrant, Richard ; et al.	2004-11-18
DRAM cell refreshment method and circuit Grant 6,801,467 - Ferrant , et al. October 5, 2	2004-10-05
Dram Grant 6,798,681 - Ferrant , et al. September 28, 2	2004-09-28
Protection circuit against voltage or current spikes, and clock circuit using a protection circuit of this kind Grant 6,765,405 - Hugues , et al. July 20, 2	2004-07-20
Amplifier for reading storage cells with exclusive-or type function App 20040036508 - Ferrant, Richard	2004-02-26
Memory circuit with dynamic redundancy App 20040017692 - Ferrant, Richard	2004-01-29
Protection circuit against voltage or current spikes, and clock circuit using a protection circuit of this kind App 20030214772 - Hugues, Jean-Francois ; et al.	2003-11-20
Dram App 20030063505 - Ferrant, Richard ; et al.	2003-04-03
Process for controlling a read access for a dynamic random access memory and corresponding memory Grant 6,538,942 - Ferrant March 25, 2	2003-03-25
DRAM cell refreshment method and circuit App 20030022427 - Ferrant, Richard ; et al.	2003-01-30
Redundancy correction ROM Grant 6,421,799 - Ferrant July 16, 2	2002-07-16
Memory Circuit Architecture App 20020018391 - FERRANT, RICHARD	2002-02-14
Process for controlling a read access for a dynamic random access memory and corresponding memory App 20020009008 - Ferrant, Richard	2002-01-24
Dynamic memory circuit including spare cells App 20020001242 - Ferrant, Richard	2002-01-03
Memory Circuit With Dynamic Redundancy App 20020001236 - FERRANT, RICHARD	2002-01-03
Highly reliable programmable monostable App 20010054913 - Ferrant, Richard	2001-12-27
Voltage regulation device for reference cell of a dynamic random access memory, reference cell, memory and associated process App 20010055220 - Ferrant, Richard	2001-12-27
One-time programmable logic cell Grant 6,205,077 - Ferrant March 20, 2	2001-03-20
Memory insensitive to disturbances Grant 5,570,313 - Masson , et al. October 29, 1	1996-10-29
Memory circuit with redundancy Grant 5,506,807 - Ferrant , et al. April 9, 1	1996-04-09
Device for the self-synchronization of the output circuits of a memory using a three-state gate Grant 4,879,693 - Ferrant November 7, 1	1989-11-07
Method for contact between two conductive or semi-conductive layers deposited on a substrate Grant 4,877,483 - Bergemont , et al. October 31, 1	1989-10-31
High reliability integrated circuit memory Grant 4,761,767 - Ferrant August 2, 1	1988-08-02
Integrated circuit memory Grant 4,707,810 - Ferrant November 17, 1	1987-11-17