loadpatents
name:-0.48038196563721
name:-0.14582204818726
name:-0.00094914436340332
Ferla; Giuseppe Patent Filings

Ferla; Giuseppe

Patent Applications and Registrations

Patent applications and USPTO patent grants for Ferla; Giuseppe.The latest application filed is for "vertical conduction power electronic device and corresponding realization method".

Company Profile
0.44.23
  • Ferla; Giuseppe - Catania N/A IT
  • Ferla; Giuseppe - Acicastello IT
  • FERLA; GIUSEPPE - Acicastello CT
  • Ferla; Giuseppe - Aci Castello IT
  • Ferla; Giuseppe - Aci Castello CT
  • Ferla, Giuseppe - Via Acicastello IT
  • Ferla; Giuseppe - Milan IT
*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.
Patent Activity
PatentDate
RF identification device with near-field-coupled antenna
Grant 9,191,072 - Finocchiaro , et al. November 17, 2
2015-11-17
RF identification device with near-field-coupled antenna
Grant 9,154,188 - Finocchiaro , et al. October 6, 2
2015-10-06
Vertical conduction power electronic device and corresponding realization method
Grant 8,895,370 - Frisina , et al. November 25, 2
2014-11-25
Vertical Conduction Power Electronic Device And Corresponding Realization Method
App 20140045309 - FRISINA; FERRUCCIO ;   et al.
2014-02-13
Vertical conduction power electronic device and corresponding realization method
Grant 8,624,332 - Frisina , et al. January 7, 2
2014-01-07
Power MOS electronic device and corresponding realizing method
Grant 8,482,085 - Magri , et al. July 9, 2
2013-07-09
Power MOS electronic device and corresponding realizing method
Grant 8,420,487 - Magri , et al. April 16, 2
2013-04-16
Rf Identification Device With Near-field-coupled Antenna
App 20120171953 - Finocchiaro; Alessandro ;   et al.
2012-07-05
Rf Identification Device With Near-field-coupled Antenna
App 20120168520 - Finocchiaro; Alessandro ;   et al.
2012-07-05
Method for manufacturing a high integration density power MOS device
Grant 8,013,384 - Arena , et al. September 6, 2
2011-09-06
Power Mos Electronic Device And Corresponding Realizing Method
App 20110089491 - Magri; Angelo ;   et al.
2011-04-21
Power Mos Electronic Device And Corresponding Realizing Method
App 20110081759 - Magri; Angelo ;   et al.
2011-04-07
Power MOS electronic device and corresponding realizing method
Grant 7,875,936 - Magri , et al. January 25, 2
2011-01-25
Method For Manufacturing A High Integration Density Power Mos Device
App 20090321826 - ARENA; Giuseppe ;   et al.
2009-12-31
Method for manufacturing a high integration density power MOS device
Grant 7,601,610 - Arena , et al. October 13, 2
2009-10-13
Switching-controlled power MOS electronic device
Grant 7,569,883 - Frisina , et al. August 4, 2
2009-08-04
Rf Identification Device With Near-field-coupled Antenna
App 20090033467 - Finocchiaro; Alessandro ;   et al.
2009-02-05
Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performance and high scaling down density
Grant 7,304,335 - Magri' , et al. December 4, 2
2007-12-04
Power MOS electronic device and corresponding realizing method
App 20060244059 - Magri; Angelo ;   et al.
2006-11-02
Switching-controlled power MOS electronic device
App 20060220121 - Frisina; Ferruccio ;   et al.
2006-10-05
Vertical-conduction And Planar-structure Mos Device With A Double Thickness Of Gate Oxide And Method For Realizing Power Vertical Mos Transistors With Improved Static And Dynamic Performance And High Scaling Down Density
App 20060186434 - MAGRI'; Angelo ;   et al.
2006-08-24
MOS power device with high integration density and manufacturing process thereof
Grant 7,091,558 - Frisina , et al. August 15, 2
2006-08-15
Method for manufacturing a high integration density power MOS device
App 20060138537 - Arena; Giuseppe ;   et al.
2006-06-29
Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density
Grant 7,067,363 - Magri' , et al. June 27, 2
2006-06-27
Vertical conduction power electronic device and corresponding realization method
App 20060071242 - Frisina; Ferruccio ;   et al.
2006-04-06
Vertical-conduction and planar-structure MOS device with a double thickness of gate oxide and method for realizing power vertical MOS transistors with improved static and dynamic performances and high scaling down density
App 20050139906 - Magri', Angelo ;   et al.
2005-06-30
Semiconductor integrated electronic device and corresponding manufacturing method
Grant 6,890,806 - Cerofolini , et al. May 10, 2
2005-05-10
MOS power device with high integration density and manufacturing process thereof
App 20040222483 - Frisina, Ferruccio ;   et al.
2004-11-11
Method for forming an interface free layer of silicon on a substrate of monocrystalline silicon
Grant 6,806,170 - Ward , et al. October 19, 2
2004-10-19
Semiconductor integrated electronic device and corresponding manufacturing method
App 20040152249 - Cerofolini, Gianfranco ;   et al.
2004-08-05
Gate insulating structure for power devices, and related manufacturing process
Grant 6,756,259 - Frisina , et al. June 29, 2
2004-06-29
Semiconductor integrated electronic device and corresponding manufacturing method
Grant 6,724,009 - Cerofolini , et al. April 20, 2
2004-04-20
Control of amount and uniformity of oxidation at the interface of an emitter region of a monocrystalline silicon wafer and a polysilicon layer formed by chemical vapor deposition
Grant 6,642,121 - Camalleri , et al. November 4, 2
2003-11-04
Method for forming an interface free layer of silicon on a substrate of monocrystalline silicon
App 20030060028 - Ward, Peter ;   et al.
2003-03-27
Semiconductor integrated electronic device and corresponding manufacturing method
App 20030049895 - Cerofolini, Gianfranco ;   et al.
2003-03-13
Control of amount and uniformity of oxidation at the interface of an emitter region of a monocrystalline silicon wafer and a polysilicon layer formed by chemical vapor deposition
App 20020155673 - Camalleri, Cateno M. ;   et al.
2002-10-24
MOS technology power device with low output resistance and low capacity, and related manufacturing process
App 20020123195 - Frisina, Ferruccio ;   et al.
2002-09-05
Gate insulating structure for power devices, and related manufacturing process
App 20020100936 - Frisina, Ferruccio ;   et al.
2002-08-01
Edge termination of semiconductor devices for high voltages with resistive voltage divider
Grant 6,365,930 - Schillaci , et al. April 2, 2
2002-04-02
Single Feature Size Mos Technology Power Device
App 20010012663 - MAGRI', ANGELO ;   et al.
2001-08-09
High Density Mos Technology Power Device
App 20010012654 - MAGRI', ANGELO ;   et al.
2001-08-09
Single Feature Size Mos Technology Power Device
App 20010011722 - FRISINA, FERRUCCIO ;   et al.
2001-08-09
MOS technology power device with low output resistance and low capacitance, and related manufacturing process
Grant 6,228,719 - Frisina , et al. May 8, 2
2001-05-08
Zero thermal budget manufacturing process for MOS-technology power devices
Grant 6,140,679 - Ferla , et al. October 31, 2
2000-10-31
Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
Grant RE36,311 - Frisina , et al. September 21, 1
1999-09-21
Zero thermal budget manufacturing process for MOS-technology power devices
Grant 5,933,733 - Ferla , et al. August 3, 1
1999-08-03
MOS-technology power device and process of making same
Grant 5,874,338 - Ferla , et al. February 23, 1
1999-02-23
Process for manufacturing a MOS-technology power device chip and package assembly
Grant 5,851,855 - Ferla , et al. December 22, 1
1998-12-22
MOS-technology power device integrated structure
Grant 5,841,167 - Grimaldi , et al. November 24, 1
1998-11-24
Process of making a MOS-technology power device
Grant 5,817,546 - Ferla , et al. October 6, 1
1998-10-06
Semiconductor electronic device with autoaligned polysilicon and silicide control terminal
Grant 5,811,335 - Santangelo , et al. September 22, 1
1998-09-22
Process for manufacturing high-density MOS-technology power devices
Grant 5,670,392 - Ferla , et al. September 23, 1
1997-09-23
MOS-technology power device chip and package assembly
Grant 5,631,476 - Ferla , et al. May 20, 1
1997-05-20
Power device integrated structure with low saturation voltage
Grant 5,631,483 - Ferla , et al. May 20, 1
1997-05-20
Electro-luminescent material, solid state electro-luminescent device and process for fabrication thereof
Grant 5,580,663 - Campisano , et al. December 3, 1
1996-12-03
Process for manufacturing an integrated bipolar power device and a fast diode
Grant 5,468,660 - Frisina , et al. November 21, 1
1995-11-21
Electronic power device having plural elementary semiconductor components connected in parallel
Grant 5,250,821 - Ferla , et al. October 5, 1
1993-10-05
Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
Grant 5,118,635 - Frisina , et al. June 2, 1
1992-06-02
Integrated high-voltage bipolar power transistor and low voltage MOS power transistor structure in the emitter switching configuration and relative manufacturing process
Grant 5,065,213 - Frisina , et al. November 12, 1
1991-11-12
Method for the manufacture of semiconductor devices with planar junctions having a variable charge concentration and a very high breakdown voltage
Grant 4,667,393 - Ferla , et al. May 26, 1
1987-05-26
Process for producing a calibrated resistance element
Grant 4,310,571 - Daniele , et al. January 12, 1
1982-01-12
Process for making CMOS field-effect transistors
Grant 4,277,291 - Cerofolini , et al. July 7, 1
1981-07-07

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