FENOUILLET-BERANGER; Claire

Patent Applications and Registrations

Patent applications and USPTO patent grants for FENOUILLET-BERANGER; Claire.The latest application filed is for "method for manufacturing a microelectronic device".

Company Profile

4.40.40

FENOUILLET-BERANGER; Claire - Grenoble Cedex 09 FR
Fenouillet-Beranger; Claire - Grenoble FR
Fenouillet-Beranger; Claire - Voiron FR
Fenouillet-Beranger; Claire - Saint Martin d'Heres FR

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Method For Manufacturing A Microelectronic Device App 20220028728 - NIEBOJEWSKI; Heimanu ; et al.	2022-01-27
Internal via with improved contact for upper semi-conductor layer of a 3D circuit Grant 10,930,562 - Fenouillet-Beranger , et al. February 23, 2	2021-02-23
Internal Via With Improved Contact For Upper Semi-conductor Layer Of A 3d Circuit App 20190371671 - FENOUILLET-BERANGER; Claire ; et al.	2019-12-05
Integrated circuit having a plurality of active layers and method of fabricating the same Grant 10,319,628 - Deprat , et al.	2019-06-11
Semiconductor and metal alloy interconnections for a 3D circuit Grant 10,199,276 - Fenouillet-Beranger , et al. Fe	2019-02-05
Method of fabrication of a FET transistor having an overlapped gate Grant 10,121,707 - Fenouillet-Beranger , et al. November 6, 2	2018-11-06
Method for fabricating auto-aligned interconnection elements for a 3D integrated circuit Grant 10,115,637 - Fenouillet-Beranger , et al. October 30, 2	2018-10-30
Device with transistors distributed over several superimposed levels integrating a resistive memory Grant 10,074,802 - Fenouillet-Beranger , et al. September 11, 2	2018-09-11
SOI integrated circuit equipped with a device for protecting against electrostatic discharges Grant 10,062,681 - Solaro , et al. August 28, 2	2018-08-28
Fabrication method of a stack of electronic devices Grant 9,997,395 - Fenouillet-Beranger , et al. June 12, 2	2018-06-12
Method For Fabricating Auto-aligned Interconnection Elements For A 3d Integrated Circuit App 20180158736 - FENOUILLET-BERANGER; Claire ; et al.	2018-06-07
Method Of Fabrication Of A Fet Transistor Having An Overlapped Gate App 20180144992 - FENOUILLET-BERANGER; Claire ; et al.	2018-05-24
Integrated Circuit Having A Plurality Of Active Layers And Method Of Fabricating The Same App 20180090366 - DEPRAT; Fabien ; et al.	2018-03-29
Superimposed transistors with auto-aligned active zone of the upper transistor Grant 9,852,950 - Fenouillet-Beranger , et al. December 26, 2	2017-12-26
Fabrication Method Of A Stack Of Electronic Devices App 20170352583 - FENOUILLET-BERANGER; Claire ; et al.	2017-12-07
Method for producing interconnections for 3D integrated circuit Grant 9,793,162 - Fenouillet-Beranger , et al. October 17, 2	2017-10-17
Fabrication method of a stack of electronic devices Grant 9,786,658 - Mathieu , et al. October 10, 2	2017-10-10
Fabrication method of a stack of electronic devices Grant 9,779,982 - Batude , et al. October 3, 2	2017-10-03
Manufacturing of self aligned interconnection elements for 3D integrated circuits Grant 9,761,583 - Fenouillet-Beranger , et al. September 12, 2	2017-09-12
Soi Integrated Circuit Equipped With A Device For Protecting Against Electrostatic Discharges App 20170256531 - Solaro; Yohann ; et al.	2017-09-07
Fabrication Method Of A Stack Of Electronic Devices App 20170178950 - BATUDE; Perrine ; et al.	2017-06-22
Fabrication Method Of A Stack Of Electronic Devices App 20170179114 - MATHIEU; Benoit ; et al.	2017-06-22
Device With Transistors Distributed Over Several Superimposed Levels Integrating A Resistive Memory App 20170162788 - FENOUILLET-BERANGER; Claire ; et al.	2017-06-08
On-SOI integrated circuit equipped with a device for protecting against electrostatic discharges Grant 9,666,577 - Solaro , et al. May 30, 2	2017-05-30
On-SOI integrated circuit comprising a lateral diode for protection against electrostatic discharges Grant 9,653,476 - Fenouillet-Beranger , et al. May 16, 2	2017-05-16
Method for producing a multilevel microelectronic structure Grant 9,646,846 - Coronel , et al. May 9, 2	2017-05-09
Semiconductor And Metal Alloy Interconnections For A 3d Circuit App 20170117186 - FENOUILLET-BERANGER; Claire ; et al.	2017-04-27
Superimposed Transistors With Auto-aligned Active Zone Ofthe Upper Transistor App 20160372375 - FENOUILLET-BERANGER; Claire ; et al.	2016-12-22
Manufacturing Of Self Aligned Interconnection Elements For 3d Integrated Circuits App 20160365342 - FENOUILLET-BERANGER; Claire ; et al.	2016-12-15
Method for producing a field effect transistor including forming a gate after forming the source and drain Grant 9,502,566 - Fenouillet-Beranger , et al. November 22, 2	2016-11-22
Integrated circuit on SOI comprising a transistor protecting from electrostatic discharges Grant 9,391,057 - Fenouillet-Beranger , et al. July 12, 2	2016-07-12
On-SOI integrated circuit comprising a subjacent protection transistor Grant 9,337,302 - Fenouillet-Beranger , et al. May 10, 2	2016-05-10
Method For Producing Interconnections For 3d Integrated Circuit App 20160111330 - FENOUILLET-BERANGER; Claire ; et al.	2016-04-21
Method For Producing A Multilevel Microelectronic Structure App 20160093504 - CORONEL; Philippe ; et al.	2016-03-31
Process for fabricating an integrated circuit having trench isolations with different depths Grant 9,275,891 - Fenouillet-Beranger , et al. March 1, 2	2016-03-01
ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges Grant 9,165,943 - Fenouillet-Beranger , et al. October 20, 2	2015-10-20
On-SOI integrated circuit comprising a triac for protection against electrostatic discharges Grant 9,165,908 - Fenouillet-Beranger , et al. October 20, 2	2015-10-20
Integrated circuit on SOI comprising a bipolar transistor with isolating trenches of distinct depths Grant 9,029,955 - Fenouillet-Beranger , et al. May 12, 2	2015-05-12
Method For Producing A Transistor App 20150084095 - FENOUILLET-BERANGER; Claire ; et al.	2015-03-26
On-SOI integrated circuit equipped with a device for protecting against electrostatic discharges App 20150061023 - Solaro; Yohann ; et al.	2015-03-05
Hybrid substrate with improved isolation and simplified method for producing a hybrid substrate Grant 8,936,993 - Fenouillet-Beranger , et al. January 20, 2	2015-01-20
Method for manufacturing a hybrid SOI/bulk semiconductor wafer Grant 8,877,600 - Fenouillet-Beranger , et al. November 4, 2	2014-11-04
Integrated Circuit On Soi Comprising A Transistor Protecting From Electrostatic Discharges App 20140319648 - Fenouillet-Beranger; Claire ; et al.	2014-10-30
Method For Manufacturing A Hybrid Soi/bulk Semiconductor Wafer App 20140170834 - Fenouillet-Beranger; Claire ; et al.	2014-06-19
Substrate provided with a semi-conducting area associated with two counter-electrodes and device comprising one such substrate Grant 8,674,443 - Coronel , et al. March 18, 2	2014-03-18
ON-SOI integrated circuit comprising a thyristor (SCR) for protection against electrostatic discharges App 20140015052 - Fenouillet-Beranger; Claire ; et al.	2014-01-16
On-SOI integrated circuit comprising a subjacent protection transistor App 20140017856 - Fenouillet-Beranger; Claire ; et al.	2014-01-16
On-SOI integrated circuit comprising a lateral diode for protection against electrostatic discharges App 20140017858 - Fenouillet-Beranger; Claire ; et al.	2014-01-16
Integrated circuit on SOI comprising a bipolar transistor with isolating trenches of distinct depths App 20140017871 - Fenouillet-Beranger; Claire ; et al.	2014-01-16
On-SOI integrated circuit comprising a triac for protection against electrostatic discharges App 20140017821 - Fenouillet-Beranger; Claire ; et al.	2014-01-16
Process for fabricating an integrated circuit having trench isolations with different depths App 20130323903 - Fenouillet-Beranger; Claire ; et al.	2013-12-05
Method for producing field effect transistors with a back gate and semiconductor device Grant 8,383,464 - Fenouillet-Beranger , et al. February 26, 2	2013-02-26
Compact field effect transistor with counter-electrode and fabrication method Grant 8,368,128 - Fenouillet-Beranger , et al. February 5, 2	2013-02-05
SRAM memory cell with four transistors provided with a counter-electrode Grant 8,314,453 - Thomas , et al. November 20, 2	2012-11-20
Substrate Provided With A Semi-conducting Area Associated With Two Counter-electrodes And Device Comprising One Such Substrate App 20110316055 - CORONEL; Philippe ; et al.	2011-12-29
Compact Field Effect Transistor With Counter-electrode And Fabrication Method App 20110298019 - FENOUILLET-BERANGER; Claire ; et al.	2011-12-08
Sram Memory Cell With Four Transistors Provided With A Counter-electrode App 20110291199 - THOMAS; Olivier ; et al.	2011-12-01
Method for producing a field effect device having self-aligned electrical connections with respect to the gate electrode Grant 8,048,751 - Fenouillet-Beranger , et al. November 1, 2	2011-11-01
Hybrid Substrate With Improved Isolation And Simplified Method For Producing A Hybrid Substrate App 20110147881 - FENOUILLET-BERANGER; Claire ; et al.	2011-06-23
Method For Producing Field Effect Transistors With A Back Gate And Semiconductor Device App 20110108942 - FENOUILLET-BERANGER; Claire ; et al.	2011-05-12
SOI transistor with self-aligned ground plane and gate and buried oxide of variable thickness Grant 7,910,419 - Fenouillet-Beranger , et al. March 22, 2	2011-03-22
Method For Producing A Field Effect Device Having Self-aligned Electrical Connections With Respect To The Gate Electrode App 20110059589 - FENOUILLET-BERANGER; Claire ; et al.	2011-03-10
MOSFET on SOI device Grant 7,804,134 - Coronel , et al. September 28, 2	2010-09-28
Process For Producing An Mos Transistor And Corresponding Integrated Circuit App 20100230755 - Coronel; Philippe ; et al.	2010-09-16
Process for producing an MOS transistor and corresponding integrated circuit Grant 7,749,858 - Coronel , et al. July 6, 2	2010-07-06
Back-lit image sensor with a uniform substrate temperature Grant 7,687,872 - Cazaux , et al. March 30, 2	2010-03-30
Manufacturing processing for an isolated transistor with strained channel Grant 7,635,615 - Barbe , et al. December 22, 2	2009-12-22
Soi Transistor With Self-aligned Ground Plane And Gate And Buried Oxide Of Variable Thickness App 20090311834 - FENOUILLET-BERANGER; Claire ; et al.	2009-12-17
Mos Transistor Manufacturing App 20090224295 - Coronel; Philippe ; et al.	2009-09-10
MOS transistor manufacturing Grant 7,556,995 - Coronel , et al. July 7, 2	2009-07-07
MOSFET on SOI device App 20080173944 - Coronel; Philippe ; et al.	2008-07-24
Manufacturing method of semiconductor-on-insulator region structures App 20080087959 - Monfray; Stephane ; et al.	2008-04-17
Back-lit image sensor with a uniform substrate temperature App 20080017946 - Cazaux; Yvon ; et al.	2008-01-24
Process for producing an MOS transistor and corresponding integrated circuit App 20070037324 - Coronel; Philippe ; et al.	2007-02-15
Manufacturing processing for an isolated transistor with strained channel App 20070001227 - Barbe; Jean-Charles ; et al.	2007-01-04
Manufacturing method of semiconductor-on-insulator region structures App 20050085026 - Monfray, Stephane ; et al.	2005-04-21

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