| Patent | Date |
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Chemically-modified graphene and method for producing the same
Grant 9,181,167 - Hua , et al. November 10, 2 | 2015-11-10 |
Chemically-modified Graphene And Method For Producing The Same
App 20130137894 - Hua; Mu-Yi ; et al. | 2013-05-30 |
Generalizations of adjoint networks techniques for RLC interconnects model-order reductions
Grant 7,797,140 - Lee , et al. September 14, 2 | 2010-09-14 |
Biomedical signal instrumentation amplifier
Grant 7,738,947 - Chow , et al. June 15, 2 | 2010-06-15 |
Method of estimating the signal delay in a VLSI circuit
Grant 7,600,206 - Lai , et al. October 6, 2 | 2009-10-06 |
Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization
Grant 7,562,324 - Chang , et al. July 14, 2 | 2009-07-14 |
Multi-point model reductions of VLSI interconnects using the rational Arnoldi method with adaptive orders
Grant 7,512,525 - Lee , et al. March 31, 2 | 2009-03-31 |
Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithm
Grant 7,509,243 - Chu , et al. March 24, 2 | 2009-03-24 |
Manufacturing Method Of High-linearity And High-power Cmos Structure
App 20080318372 - Chiu; Hsien-Chin ; et al. | 2008-12-25 |
Interconnect model-order reduction method
Grant 7,437,689 - Chu , et al. October 14, 2 | 2008-10-14 |
Method of estimating the signal delay in a VLSI circuit
App 20080250369 - Lai; Ming-Hong ; et al. | 2008-10-09 |
Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design
Grant 7,398,499 - Lai , et al. July 8, 2 | 2008-07-08 |
High-linearity and high-power CMOS structure and manufacturing method for the same
App 20080157210 - Chiu; Hsien-Chin ; et al. | 2008-07-03 |
Method of reducing a multiple-inputs multiple-outputs (MIMO) interconnect circuit system in a global lanczos algorithm
App 20080126028 - Chu; Chia-Chi ; et al. | 2008-05-29 |
Method of designing a synchronous circuit of VLSI for clock skew scheduling and optimization
App 20080115098 - Chang; Chao-Kai ; et al. | 2008-05-15 |
Efficient digital filter design tool for approximating an FIR filter with a low-order linear-phase IIR filter
Grant 7,373,367 - Lee , et al. May 13, 2 | 2008-05-13 |
Method of searching paths suffering from the electrostatic discharge in the process of an integrated circuit design
App 20070277138 - Lai; Ming-Hong ; et al. | 2007-11-29 |
Biomedical signal instrumentation amplifier
App 20070260150 - Chow; Hwang-Cherng ; et al. | 2007-11-08 |
Method of developing an analogical VLSI macro model in a global Arnoldi algorithm
App 20070255538 - Chu; Chia-Chi ; et al. | 2007-11-01 |
Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops
Grant 7,254,790 - Lee , et al. August 7, 2 | 2007-08-07 |
Clock tree synthesis for low power consumption and low clock skew
Grant 7,216,322 - Lai , et al. May 8, 2 | 2007-05-08 |
Method and apparatus for model-order reduction and sensitivity analysis
Grant 7,216,309 - Lee , et al. May 8, 2 | 2007-05-08 |
Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration
Grant 7,191,418 - Lee , et al. March 13, 2 | 2007-03-13 |
Method on scan chain reordering for lowering VLSI power consumption
Grant 7,181,664 - Lee , et al. February 20, 2 | 2007-02-20 |
Interconnect model-order reduction method
App 20070033549 - Chu; Chia-Chi ; et al. | 2007-02-08 |
Method of determining high-speed VLSI reduced-order interconnect by non-symmetric lanczos algorithm
App 20060282799 - Chu; Chia-Chi ; et al. | 2006-12-14 |
Method of estimating crosstalk noise in lumped RLC coupled interconnects
Grant 7,124,381 - Lee , et al. October 17, 2 | 2006-10-17 |
Multi-point model reductions of VLSI interconnects using the rational arnoldi method with adaptive orders
App 20060149525 - Lee; Herng-Jer ; et al. | 2006-07-06 |
Generalizations of adjoint networks techniques for RLC interconnects model-order reductions
App 20060100831 - Lee; Herng-Jer ; et al. | 2006-05-11 |
Moment computations of nonuniform distributed coupled RLC trees with applications to estimating crosstalk noise
App 20060100830 - Lee; Herng-Jer ; et al. | 2006-05-11 |
Method of verification of estimating crosstalk noise in coupled RLC interconnects with distributed line in nanometer integrated circuits
Grant 7,017,130 - Lee , et al. March 21, 2 | 2006-03-21 |
Clock tree synthesis for low power consumption and low clock skew
App 20060053395 - Lai; Ming-Hong ; et al. | 2006-03-09 |
Method of moment computations in R(L)C interconnects of high speed VLSI with resistor loops
App 20060015832 - Lee; Herng-Jer ; et al. | 2006-01-19 |
Method and apparatus for rapidly selecting types of buffers which are inserted into the clock tree for high-speed very-large-scale-integration
App 20060010414 - Lee; Herng-Jer ; et al. | 2006-01-12 |
Method Of Verification Of Estimating Crosstalk Noise In Coupled Rlc Interconnects With Distributed Line In Nanometer Integrated Circuits
App 20060010406 - Lee; Herng-Jer ; et al. | 2006-01-12 |
Method of estimating crosstalk noise in lumped RLC coupled interconnects
App 20050278668 - Lee, Herng-Jer ; et al. | 2005-12-15 |
Efficient digital filter design tool for approximating an FIR filter with a low-order linear-phase IIR filter
App 20050235023 - Lee, Herng-Jer ; et al. | 2005-10-20 |
Method on scan chain reordering for lowering VLSI power consumption
App 20050235182 - Lee, Herng-Jer ; et al. | 2005-10-20 |
Method and apparatus for model-order reduction and sensitivity analysis
App 20040261042 - Lee, Herng-Jer ; et al. | 2004-12-23 |
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