Feiste; Kurt Alan

Patent Applications and Registrations

Patent applications and USPTO patent grants for Feiste; Kurt Alan.The latest application filed is for "method to detect a stalled instruction stream and serialize micro-operation execution".

Company Profile

0.15.10

Feiste; Kurt Alan - Austin TX

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Generating a flush vector from a first execution unit directly to every other execution unit of a plurality of execution units in order to block all register updates Grant 8,082,423 - Abernathy , et al. December 20, 2	2011-12-20
Method and apparatus for delaying a load miss flush until issuing the dependent instruction Grant 7,953,960 - Feiste , et al. May 31, 2	2011-05-31
Method to Detect a Stalled Instruction Stream and Serialize Micro-Operation Execution App 20080294885 - Feiste; Kurt Alan	2008-11-27
Method to detect a stalled instruction stream and serialize micro-operation execution Grant 7,412,589 - Feiste August 12, 2	2008-08-12
High Frequency Stall Design App 20080148021 - DeMent; Jonathan James ; et al.	2008-06-19
System and method for high frequency stall design Grant 7,370,176 - DeMent , et al. May 6, 2	2008-05-06
Method and apparatus for issuing instructions from an issue queue in an information handling system Grant 7,350,056 - Abernathy , et al. March 25, 2	2008-03-25
Method to Detect a Stalled Instruction Stream and Serialize Micro-Operation Execution App 20070234018 - Feiste; Kurt Alan	2007-10-04
Method and apparatus for distributing flush instructions App 20070198814 - Abernathy; Christopher Michael ; et al.	2007-08-23
Method and apparatus for issuing instructions from an issue queue including a main issue queue array and an auxiliary issue queue array in an information handling system App 20070198812 - Abernathy; Christopher Michael ; et al.	2007-08-23
Method and apparatus for delaying a load miss flush until issuing the dependent instruction App 20070088935 - Feiste; Kurt Alan ; et al.	2007-04-19
Method and apparatus for issuing instructions from an issue queue in an information handling system App 20070074005 - Abernathy; Christopher Michael ; et al.	2007-03-29
System and method for high frequency stall design App 20070043931 - DeMent; Jonathan James ; et al.	2007-02-22
System and method for handling multi-cycle non-pipelined instruction sequencing App 20060224864 - DeMent; Jonathan James ; et al.	2006-10-05
Multithreading recycle and dispatch mechanism App 20040111594 - Feiste, Kurt Alan ; et al.	2004-06-10
Mechanism to reduce instruction cache miss penalties and methods therefor Grant 6,658,534 - White , et al. December 2, 2	2003-12-02
System and method for executing and completing store instructions Grant 6,134,646 - Feiste , et al. October 17, 2	2000-10-17
Method and apparatus for detecting overlap condition between a storage instruction and previously executed storage reference instruction Grant 6,070,238 - Feiste , et al. May 30, 2	2000-05-30
Forwarding store instruction result to load instruction with reduced stall or flushing by effective/real data address bytes matching Grant 6,021,485 - Feiste , et al. February 1, 2	2000-02-01
Data processing system and method of operation having input/output drivers with reduced power consumption and noise levels Grant 5,974,259 - Casal , et al. October 26, 1	1999-10-26
High level (L2) cache and method for efficiently updating directory entries utilizing an n-position priority queue and priority indicators Grant 5,963,978 - Feiste October 5, 1	1999-10-05
Data processing system and method for maintaining coherency between high and low level caches using inclusive states Grant 5,926,830 - Feiste July 20, 1	1999-07-20
Pipelined flushing of a high level cache and invalidation of lower level caches Grant 5,860,100 - Feiste , et al. January 12, 1	1999-01-12
Resolving processor and system bus address collision in a high-level cache Grant 5,832,276 - Feiste , et al. November 3, 1	1998-11-03
System and method for resolving contention arising from execution of cache coherency operations in a multiple cache computer system Grant 5,822,765 - Boatright , et al. October 13, 1	1998-10-13

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