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Instruction dispatch routing
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Processor providing intelligent management of values buffered in overlaid architected and non-architected register files
Grant 11,327,757 - Battle , et al. May 10, 2 | 2022-05-10 |
Instruction Dispatch Routing
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Processor Providing Intelligent Management Of Values Buffered In Overlaid Architected And Non-architected Register Files
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Redistribution of architected states for a processor register file
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Parallel dispatching of multi-operation instructions in a multi-slice computer processor
Grant 10,970,079 - Feiste , et al. April 6, 2 | 2021-04-06 |
Instruction chaining
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Dispatching, allocating, and deallocating instructions with real/virtual and region tags in a queue in a processor
Grant 10,877,763 - Lloyd , et al. December 29, 2 | 2020-12-29 |
Parallel slice processor shadowing states of hardware threads across execution slices
Grant 10,838,728 - Feiste , et al. November 17, 2 | 2020-11-17 |
Operation of a multi-slice processor implementing load-hit-store handling
Grant 10,740,107 - Ayub , et al. A | 2020-08-11 |
Instruction Chaining
App 20200249954 - Kind Code | 2020-08-06 |
Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core
Grant 10,671,399 - Boersma , et al. | 2020-06-02 |
Low-overhead, low-latency operand dependency tracking for instructions operating on register pairs in a processor core
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Parallel Dispatching Of Multi-operation Instructions In A Multi-slice Computer Processor
App 20200042320 - FEISTE; KURT A. ; et al. | 2020-02-06 |
Dispatching, Allocating, and Deallocating Instructions in a Queue in a Processor
App 20200042319 - Lloyd; Bryan ; et al. | 2020-02-06 |
Parallel dispatching of multi-operation instructions in a multi-slice computer processor
Grant 10,496,412 - Feiste , et al. De | 2019-12-03 |
Operation of a multi-slice processor implementing datapath steering
Grant 10,437,756 - Carlough , et al. O | 2019-10-08 |
Operation Of A Multi-slice Processor Implementing Datapath Steering
App 20190294571 - CARLOUGH; STEVEN R. ; et al. | 2019-09-26 |
Operation of a multi-slice processor implementing datapath steering
Grant 10,417,152 - Carlough , et al. Sept | 2019-09-17 |
Low-overhead, Low-latency Operand Dependency Tracking For Instructions Operating On Register Pairs In A Processor Core
App 20190042268 - Boersma; Maarten J. ; et al. | 2019-02-07 |
Low-overhead, Low-latency Operand Dependency Tracking For Instructions Operating On Register Pairs In A Processor Core
App 20190042267 - Boersma; Maarten J. ; et al. | 2019-02-07 |
Rotational Dispatch For Parallel Slice Processor
App 20190026112 - Feiste; Kurt A. ; et al. | 2019-01-24 |
Supporting even instruction tag (`ITAG`) requirements in a multi-slice processor using null internal operations (IOPs)
Grant 10,120,683 - Carlough , et al. November 6, 2 | 2018-11-06 |
Parallel slice processor shadowing states of hardware threads across execution slices
Grant 10,102,001 - Feiste , et al. October 16, 2 | 2018-10-16 |
Parallel Slice Processor Shadowing States Of Hardware Threads Across Execution Slices
App 20180217842 - Feiste; Kurt A. ; et al. | 2018-08-02 |
Execution slice with supplemental instruction port for an instruction using a source operand from another instruction port
Grant 9,977,677 - Feiste , et al. May 22, 2 | 2018-05-22 |
Operation of a multi-slice processor with history buffers storing transaction memory state information
Grant 9,971,687 - Barrick , et al. May 15, 2 | 2018-05-15 |
Operation Of A Multi-slice Processor Implementing Instruction Fusion
App 20180107510 - CARLOUGH; STEVEN R. ; et al. | 2018-04-19 |
Administering Instruction Tags In A Computer Processor
App 20180004516 - FEISTE; KURT A. ; et al. | 2018-01-04 |
Operation Of A Multi-slice Processor Implementing Load-hit-store Handling
App 20170351522 - AYUB; SALMA ; et al. | 2017-12-07 |
Operation Of A Multi-slice Processor Implementing Datapath Steering
App 20170351523 - CARLOUGH; STEVEN R. ; et al. | 2017-12-07 |
Operation Of A Multi-slice Processor Implementing Datapath Steering
App 20170351524 - CARLOUGH; STEVEN R. ; et al. | 2017-12-07 |
Supporting Even Instruction Tag ('itag') Requirements In A Multi-slice Processor Using Null Internal Operations (iops)
App 20170315809 - CARLOUGH; STEVEN R. ; et al. | 2017-11-02 |
Rotational Dispatch For Parallel Slice Processor
App 20170293488 - Feiste; Kurt A. ; et al. | 2017-10-12 |
Operation Of A Multi-slice Processor With History Buffers Storing Transaction Memory State Information
App 20170235674 - BARRICK; BRIAN D. ; et al. | 2017-08-17 |
Parallel Dispatching Of Multi-operation Instructions In A Multi-slice Computer Processor
App 20170228234 - FEISTE; KURT A. ; et al. | 2017-08-10 |
Issue unit for placing a processor into a gradual slow mode of operation
Grant 8,200,946 - Abernathy , et al. June 12, 2 | 2012-06-12 |
Information handling system with real and virtual load/store instruction issue queue
Grant 8,041,928 - Burky , et al. October 18, 2 | 2011-10-18 |
Method and system for determining multiple unused registers in a processor
Grant 7,949,857 - Feiste May 24, 2 | 2011-05-24 |
Processor livelock recovery by gradual stalling of instruction processing rate during detection of livelock condition
Grant 7,818,544 - Abernathy , et al. October 19, 2 | 2010-10-19 |
Information Handling System With Real And Virtual Load/store Instruction Issue Queue
App 20100161945 - Burky; William E. ; et al. | 2010-06-24 |
Method And System For Determining Multiple Unused Registers In A Processor
App 20090259815 - FEISTE; KURT A. | 2009-10-15 |
Issue Unit for Placing a Processor into a Gradual Slow Mode of Operation
App 20090006820 - Abernathy; Christopher M. ; et al. | 2009-01-01 |
Mechanisms for Placing a Processor into a Gradual Slow Mode of Operation
App 20090006817 - Abernathy; Christopher M. ; et al. | 2009-01-01 |
Issue unit for placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
Grant 7,437,539 - Abernathy , et al. October 14, 2 | 2008-10-14 |
Placing a processor into a gradual slow mode of operation in response to a detected livelock condition within a processor pipeline
Grant 7,434,033 - Abernathy , et al. October 7, 2 | 2008-10-07 |
Issue Unit For Placing A Processor Into A Gradual Slow Mode Of Operation
App 20070245129 - Abernathy; Christopher M. ; et al. | 2007-10-18 |
System And Method For Placing A Processor Into A Gradual Slow Mode Of Operation
App 20070245350 - Abernathy; Christopher M. ; et al. | 2007-10-18 |
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