Feilchenfeld; Natalie B.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Feilchenfeld; Natalie B..The latest application filed is for "lateral pin diodes and schottky diodes".

Company Profile

2.34.30

Feilchenfeld; Natalie B. - Jericho VT
Feilchenfeld; Natalie B - Jericho VT
Feilchenfeld; Natalie B. - Endicott NY

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Lateral PiN diodes and schottky diodes Grant 10,535,551 - Feilchenfeld , et al. Ja	2020-01-14
Device structures for a silicon-on-insulator substrate with a high-resistance handle wafer Grant 10,446,644 - Camillo-Castillo , et al. Oc	2019-10-15
Tapered gate oxide in LDMOS devices Grant 10,050,115 - Brown , et al. August 14, 2	2018-08-14
LATERAL PiN DIODES AND SCHOTTKY DIODES App 20180204761 - FEILCHENFELD; Natalie B. ; et al.	2018-07-19
Lateral PiN diodes and schottky diodes Grant 9,947,573 - Feilchenfeld , et al. April 17, 2	2018-04-17
Structures with contact trenches and isolation trenches Grant 9,893,157 - Feilchenfeld , et al. February 13, 2	2018-02-13
Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure Grant 9,799,652 - Feilchenfeld , et al. October 24, 2	2017-10-24
Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method Grant 9,786,606 - Feilchenfeld , et al. October 10, 2	2017-10-10
Semiconductor structure with a dopant implant region having a linearly graded conductivity level and method of forming the structure Grant 9,768,028 - Feilchenfeld , et al. September 19, 2	2017-09-19
Dual shallow trench isolation (STI) structure for field effect transistor (FET) Grant 9,595,579 - Feilchenfeld , et al. March 14, 2	2017-03-14
Device Structures For A Silicon-on-insulator Substrate With A High-resistance Handle Wafer App 20160372582 - Camillo-Castillo; Renata ; et al.	2016-12-22
Tapered Gate Oxide In Ldmos Devices App 20160190269 - Brown; Brennan J. ; et al.	2016-06-30
Semiconductor Structures With Isolated Ohmic Trenches And Stand-alone Isolation Trenches And Related Method App 20160190067 - Feilchenfeld; Natalie B. ; et al.	2016-06-30
Semiconductor structures with isolated ohmic trenches and stand-alone isolation trenches and related method Grant 9,324,632 - Feilchenfeld , et al. April 26, 2	2016-04-26
LATERAL PiN DIODES AND SCHOTTKY DIODES App 20160064475 - FEILCHENFELD; Natalie B. ; et al.	2016-03-03
Self-aligned Bipolar Junction Transistor Having Self-planarizing Isolation Raised Base Structures App 20160043202 - Feilchenfeld; Natalie B. ; et al.	2016-02-11
Semiconductor Structures With Isolated Ohmic Trenches And Stand-alone Isolation Trenches And Related Method App 20150348870 - Feilchenfeld; Natalie B. ; et al.	2015-12-03
Self-aligned bipolar junction transistor having self-planarizing isolation raised base structures Grant 9,202,869 - Feilchenfeld , et al. December 1, 2	2015-12-01
Dual Shallow Trench Isolation (sti) Field Effect Transistor (fet) And Methods Of Forming App 20150255539 - Feilchenfeld; Natalie B. ; et al.	2015-09-10
High voltage laterally diffused metal oxide semiconductor Grant 9,059,276 - Feilchenfeld , et al. June 16, 2	2015-06-16
Lateral diffusion field effect transistor with drain region self-aligned to gate electrode Grant 8,946,013 - Feilchenfeld , et al. February 3, 2	2015-02-03
Interdigitated capacitors with a zero quadratic voltage coefficient of capacitance or zero linear temperature coefficient of capacitance Grant 8,901,710 - Anderson , et al. December 2, 2	2014-12-02
High Voltage Laterally Diffused Metal Oxide Semiconductor App 20140346597 - Feilchenfeld; Natalie B. ; et al.	2014-11-27
Self-aligned Bipolar Junction Transistor Having Self-planarizing Isolation Raised Base Structures App 20140332927 - FEILCHENFELD; NATALIE B. ; et al.	2014-11-13
Dual Shallow Trench Isolation (sti) Field Effect Transistor (fet) And Methods Of Forming App 20140327084 - Feilchenfeld; Natalie B. ; et al.	2014-11-06
Interdigitated Capacitors With A Zero Quadratic Voltage Coefficient Of Capacitance Or Zero Linear Temperature Coefficient Of Capacitance App 20140239448 - Anderson; Frederick G. ; et al.	2014-08-28
Isolated zener diode, an integrated circuit incorporating multiple instances of the zener diode, a method of forming the zener diode and a design structure for the zener diode Grant 8,796,108 - Anderson , et al. August 5, 2	2014-08-05
Isolated Zener Diode, An Integrated Circuit Incorporating Multiple Instances Of The Zener Diode, A Method Of Forming The Zener Diode And A Design Structure For The Zener Diode App 20130299938 - Anderson; Frederick G. ; et al.	2013-11-14
Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration Grant 8,525,293 - Feilchenfeld , et al. September 3, 2	2013-09-03
Isolated Zener diode Grant 8,492,866 - Anderson , et al. July 23, 2	2013-07-23
Isolated Zener Diode App 20130175656 - Anderson; Frederick G. ; et al.	2013-07-11
Bipolar Transistor With Raised Extrinsic Self-aligned Base Using Selective Epitaxial Growth For Bicmos Integration App 20120319233 - Feilchenfeld; Natalie B. ; et al.	2012-12-20
Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration Grant 8,236,662 - Feilchenfeld , et al. August 7, 2	2012-08-07
Method and structure for creation of a metal insulator metal capacitor Grant 8,227,849 - Eshun , et al. July 24, 2	2012-07-24
Lateral Diffusion Field Effect Transistor With Drain Region Self-aligned To Gate Electrode App 20120126319 - Feilchenfeld; Natalie B. ; et al.	2012-05-24
Lateral diffusion field effect transistor with drain region self-aligned to gate electrode Grant 8,114,750 - Feilchenfeld , et al. February 14, 2	2012-02-14
Lateral diffusion field effect transistor with a trench field plate Grant 7,956,412 - Feilchenfeld , et al. June 7, 2	2011-06-07
Bipolar Transistor With Raised Extrinsic Self-aligned Base Using Selective Epitaxial Growth For Bicmos Integration App 20110062548 - Feilchenfeld; Natalie B. ; et al.	2011-03-17
Bipolar transistor with raised extrinsic self-aligned base using selective epitaxial growth for BiCMOS integration Grant 7,892,910 - Feilchenfeld , et al. February 22, 2	2011-02-22
Modifying layout of IC based on function of interconnect and related circuit and design structure Grant 7,886,240 - Adkisson , et al. February 8, 2	2011-02-08
Optimized device isolation Grant 7,868,423 - Benoit , et al. January 11, 2	2011-01-11
Lateral diffusion field effect transistor with asymmetric gate dielectric profile Grant 7,829,945 - Adkisson , et al. November 9, 2	2010-11-09
Method And Structure For Creation Of A Metal Insulator Metal Capacitor App 20100149723 - ESHUN; EBENEZER E. ; et al.	2010-06-17
Method and structure for creation of a metal insulator metal capacitor Grant 7,728,372 - Eshun , et al. June 1, 2	2010-06-01
Optimized Device Isolation App 20100117122 - Benoit; John J. ; et al.	2010-05-13
Lateral Diffusion Field Effect Transistor With Drain Region Self-aligned To Gate Electrode App 20090261426 - Feilchenfeld; Natalie B. ; et al.	2009-10-22
Modifying Layout Of Ic Based On Function Of Interconnect And Related Circuit And Design Structure App 20090193378 - Adkisson; James W. ; et al.	2009-07-30
Lateral Diffusion Field Effect Transistor With A Trench Field Plate App 20090140343 - Feilchenfeld; Natalie B. ; et al.	2009-06-04
Lateral Diffusion Field Effect Transistor With Asymmetric Gate Dielectric Profile App 20090108347 - Adkisson; James W. ; et al.	2009-04-30
Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask Grant 7,511,940 - Coolbaugh , et al. March 31, 2	2009-03-31
Bipolar Transistor With Raised Extrinsic Self-aligned Base Using Selective Epitaxial Growth For Bicmos Integration App 20080203490 - Feilchenfeld; Natalie B. ; et al.	2008-08-28
Formation Of Metal-insulator-metal Capacitor Simultaneously With Aluminum Metal Wiring Level Using A Hardmask App 20080019077 - Coolbaugh; Douglas D. ; et al.	2008-01-24
Formation of metal-insulator-metal capacitor simultaneously with aluminum metal wiring level using a hardmask Grant 7,301,752 - Coolbaugh , et al. November 27, 2	2007-11-27
Method And Structure For Creation Of A Metal Insulator Metal Capacitor App 20070262416 - Eshun; Ebenezer E. ; et al.	2007-11-15
Formation Of Metal-insulator-metal Capacitor Simultaneously With Aluminum Metal Wiring Level Using A Hardmask App 20050272219 - Coolbaugh, Douglas D. ; et al.	2005-12-08
Method to fabricate high-performance NPN transistors in a BiCMOS process Grant 6,906,401 - Dunn , et al. June 14, 2	2005-06-14
Method to fabricate high-performance NPN transistors in a BiCMOS process App 20040224461 - Dunn, James S. ; et al.	2004-11-11
Method To Fabricate High-performance Npn Transistors In A Bicmos Process App 20040222497 - Dunn, James S. ; et al.	2004-11-11
Method to fabricate high-performance NPN transistors in a BiCMOS process Grant 6,809,024 - Dunn , et al. October 26, 2	2004-10-26
Forming a polymide pattern on a substrate Grant 4,883,744 - Feilchenfeld , et al. November 28, 1	1989-11-28

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.